Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Shu-Yi Kao"'
Autor:
Shu-Yi Kao, 高樹頤
100
Various V-band CMOS 360° active phase shifters were designed in this thesis for the applications in beam-steering phased array systems. Typical full 360° phase shifters have a large loss variation when the phase is tuned. This induces a si
Various V-band CMOS 360° active phase shifters were designed in this thesis for the applications in beam-steering phased array systems. Typical full 360° phase shifters have a large loss variation when the phase is tuned. This induces a si
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/69571248288031291947
Autor:
Shu-Yi Kao, 高淑怡
87
Diffusion layer is an important part of symmetric key block cipher. With the ability of diffusion layer, the change of every plaintext bit or every key bit affects every output bit. It also increases the difficulty of attack methods. The diff
Diffusion layer is an important part of symmetric key block cipher. With the ability of diffusion layer, the change of every plaintext bit or every key bit affects every output bit. It also increases the difficulty of attack methods. The diff
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/23167371245834621921
Autor:
Chia-Heng Yen, Chun-Teng Chen, Cheng-Yen Wen, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. :1-1
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::02afe6b42f9cead23055f025e3641d05
https://doi.org/10.1109/tcad.2023.3253043
https://doi.org/10.1109/tcad.2023.3253043
Autor:
Ying-Yen Chen, Chun-Teng Chen, Shu-Yi Kao, Mango C.-T. Chao, Jih-Nung Lee, Kai-Chiang Wu, Chia-Heng Yen, Mason Chern, Ting-Rui Wang, Cheng-Hao Yang
Publikováno v:
VTS
GDBN (good die in bad neighborhood) methodology has been regarded as an effective technique for reducing DPPM (defect parts per million), by identifying and rejecting suspicious dice even though they test good. Instead of examining eight immediate ne
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5dbfdd9e9dcb1ae2db77e6feda887538
https://doi.org/10.1109/vts50974.2021.9441055
https://doi.org/10.1109/vts50974.2021.9441055
Autor:
Cheng-Yen Wen, Kai-Chiang Wu, Chun-Teng Chen, Ying-Yen Chen, Shu-Yi Kao, Mango C.-T. Chao, Jih-Nung Lee, Chia-Heng Yen, Mason Chern, Cheng-Hao Yang, Chun-Yi Kuo
Publikováno v:
VTS
In order to reduce DPPM (defect parts per million), IDDQ testing methodology can be exploited for identifying "outliers" which are potentially defective but not detected by signoff functional and parametric tests. Conventional IDDQ testing paradigms
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ed924617520fdeca42395d437df2a594
https://doi.org/10.1109/vts48691.2020.9107570
https://doi.org/10.1109/vts48691.2020.9107570
Autor:
Kai-Chiang Wu, Yu-Teng Nien, Mango C.-T. Chao, Ying-Yen Chen, Shu-Yi Kao, Dong-Zhen Lee, Mason Chern, Chen Po-Lin, Jih-Nung Lee
Publikováno v:
ITC
In order to reduce DPPM (defect parts per million), cell-aware (CA) methodology was proposed to cover various types of intra-cell defects. The resulting CA faults can be a 1-time-frame (1tf) or 2-time-frame (2tf) fault, and 2tf CA tests were experime
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4c9fef8c7b2480ca5f9a96144a6e6d65
https://doi.org/10.1109/itc44170.2019.9000119
https://doi.org/10.1109/itc44170.2019.9000119
Publikováno v:
VLSI-DAT
Using speed sensor to find out the unexpected process variation and design performance degradation is getting more and more attention. In this paper, we demonstrate the industrial case of identifying process variation, with the power of in-house deve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::215e652af6c12128c9bbda047a3c4746
https://doi.org/10.1109/vlsi-dat.2015.7114548
https://doi.org/10.1109/vlsi-dat.2015.7114548
Publikováno v:
Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.
Engineering Change Order (ECO) routing is often requested in later design stages even after chip manufacturing. We propose an ECO routing method that can reuse most existing routing pattern to implement the modifications. In current industrial design
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8ff7a49e8bcfabc0ba49f08dba5c1893
https://doi.org/10.1109/vdat.2010.5496675
https://doi.org/10.1109/vdat.2010.5496675