Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Shriram D. Moharil"'
Autor:
Kevin Scholz, S M Stalin, Robert DeMoor, Tapobrata Bandyopadhyay, Snehamay Sinha, Shriram D. Moharil
Publikováno v:
2017 IEEE 21st Workshop on Signal and Power Integrity (SPI).
This paper presents a case study of DDR3 interface timing jitter of a DDR subsystem on an evaluation module. The total jitter was separated into various Signal Integrity (SI) and Power Integrity (PI) effects, including signal crosstalk, impedance dis
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7ba0ef71d6d13129b948eb74ea76b260
https://doi.org/10.1109/sapiw.2017.7944019
https://doi.org/10.1109/sapiw.2017.7944019
Autor:
Michael C. Gill, Oluleye Olorode, Raguram Damodaran, Rama Venkatasubramanian, S. Mullinnix, Dheera Balasubramanian, Naveen Bhoria, Kyle Peavy, Nuruddin Mahmood, Hung Ong, Alan Hales, Krishna Chaithanya Gurram, Shriram D. Moharil, Arjun Rajagopal, David Matthew Thompson, Jonathan (Son) Hung Tran, Jose Luis Flores, Robert Sussman, Timothy D. Anderson, Matthew D. Pierson, Sanjive Agarwala, Soujanya Narnur, Duc Quang Bui, Wu Daniel, Abhijeet Ashok Chachad, Mujibur Rahman, Anthony M. Hill, Dhileep Gopalakrishnan
Publikováno v:
VLSI Design
The next-generation C66x DSP integrated fixed and floating-point DSP implemented in TSMC 40nm process is presented in this paper. The DSP core runs at 1.25GHz at 0.9V and has a standby power consumption of 800mW. The core transistor count is 21.5 mil
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2c3e462f0cea41a8b6eda492b12f155b
https://doi.org/10.1109/vlsid.2012.85
https://doi.org/10.1109/vlsid.2012.85
Autor:
Eric Biscondi, Peter Richard Dent, Hasan Mahmood, Anthony J. Lell, Soujanya Narnur, Timothy D. Anderson, Mingjian Yan, Shriram D. Moharil, Ashish Shrivastava, Duc Quang Bui, Mujibur Rahman
Publikováno v:
IEEE Symposium on Computer Arithmetic
A next generation VLIW DSP Central Processing Unit (CPU) which has an integrated fixed point and floating point Instruction Set Architecture (ISA) is presented. It is designed to meet a 1.5 GHz core clock frequency in a 40nm process with aggressive a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fce6968700c04b89ddb52aa058936d7c
https://doi.org/10.1109/arith.2011.20
https://doi.org/10.1109/arith.2011.20