Zobrazeno 1 - 10
of 84
pro vyhledávání: '"Shoumian, Chen"'
Autor:
Zhidong Tang, Zewei Wang, Ao Guo, Linlin Liu, Chengwei Cao, Xin Luo, Weican Wu, Yingjia Guo, Zhenghang Zhi, Yongqi Hu, Yongfeng Cao, Ganbing Shang, Liujiang Yu, Shaojian Hu, Shoumian Chen, Yuhang Zhao, Xufeng Kou
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 10, Pp 532-539 (2022)
This paper presents experimental RF characterizations and modeling on the nano-scale multi-finger gate MOSFETs of the HLMC 40 nm low-power CMOS technology. Both the resistive and capacitive components in the equivalent circuit model for the RF MOSFET
Externí odkaz:
https://doaj.org/article/64806c3822b04a9f86c3c7a26f70b54c
Publikováno v:
Journal of Microelectronic Manufacturing, Vol 3, Iss 1, Pp 1-6 (2020)
5 nm logic process is the current leading-edge technology which is under development in world-wide leading foundries. In a typical 5 nm logic process, the Fin pitch is 22~27 nm, the contact-poly pitch (CPP) is 48~55 nm, and the minimum metal pitch (M
Externí odkaz:
https://doaj.org/article/474c8b581eac4d3b8d17bf3cf05bafa7
Publikováno v:
Journal of Microelectronic Manufacturing, Vol 3, Iss 1, Pp 1-6 (2020)
With the continuous scaling in conventional CMOS technologies, the planar MOSFET device is limited by the severe short-channel-effect (SCE), Multi-gate FETs (MuG-FET) such as FinFETs and Nanowire, Nanosheet devices have emerged as the most promising
Externí odkaz:
https://doaj.org/article/cbc0c74569e240d19fbd945b23fbc48f
Publikováno v:
Journal of Microelectronic Manufacturing, Vol 2, Iss 3, Pp 1-7 (2019)
5 nm logic technology node is believed to be the first node that will adopt Extremely Ultra-Violet (EUV) lithography on a large scale. We have done a simulation study for typical 5 nm logic design rule patterns. In a 5 nm logic photo process, the mos
Externí odkaz:
https://doaj.org/article/5f318bd855fe487cb79f486943cc8376
Autor:
Tao Zhou, Xuelong Shi, Chen Li, Yan Yan, Bowen Xu, Shoumian Chen, Yuhang Zhao, Wenzhan Zhou, Kan Zhou, Xuan Zeng
Publikováno v:
Journal of Microelectronic Manufacturing, Vol 4, Iss 1 (2021)
Scanning electron microscope (SEM) metrology is critical in semiconductor manufacturing for patterning process quality assessment and monitoring. Besides feature width and feature-feature space dimension measurements from critical dimension SEM (CDSE
Externí odkaz:
https://doaj.org/article/65aae1c1f8b2454e857026f76813a406
Publikováno v:
Journal of Microelectronic Manufacturing, Vol 3, Iss 4 (2020)
Inverse lithography technology (ILT) is intended to achieve optimal mask design to print a lithography target for a given lithography process. Full chip implementation of rigorous inverse lithography remains a challenging task because of enormous com
Externí odkaz:
https://doaj.org/article/e37608cd98d645ce962f572581667750
Publikováno v:
Journal of Microelectronic Manufacturing, Vol 2, Iss 4 (2019)
In 5 nm technology node, FinFET device performance is sensitive to the dimension of the device structure such as the fin profile. In this work, we simulate the influence of fin height and fin width to an n-type FinFET. We have found that an optimized
Externí odkaz:
https://doaj.org/article/8fc53787488b49e9b2530761fde87837
Autor:
Yongqi Hu, Zewei Wang, Renhe Chen, Zhidong Tang, Ao Guo, Chengwei Cao, Weican Wu, Shoumian Chen, Yuhang Zhao, Liujiang Yu, Ganbing Shang, Hao Xu, Shaojian Hu, Xufeng Kou
Publikováno v:
2022 IEEE International Symposium on Circuits and Systems (ISCAS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2a67eda864a34f4e5924071d57d3e61e
https://doi.org/10.1109/iscas48785.2022.9937477
https://doi.org/10.1109/iscas48785.2022.9937477
Autor:
Xuan Zeng, Bowen Xu, Kan Zhou, Yuhang Zhao, Wenzhan Zhou, Shoumian Chen, Chen Li, Shi Xuelong, Tao Zhou, Yan Yan
Publikováno v:
Journal of Microelectronic Manufacturing, Vol 4, Iss 1 (2021)
Scanning electron microscope (SEM) metrology is critical in semiconductor manufacturing for patterning process quality assessment and monitoring. Besides feature width and feature-feature space dimension measurements from critical dimension SEM (CDSE
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::01a010a418870e0fcb1b01f5713551db
https://doi.org/10.33079/jomm.21040102
https://doi.org/10.33079/jomm.21040102
Autor:
Yongfeng Cao, Xiuhao Zhang, Zewei Wang, Jialun Li, Lingge Liu, Xin Luo, Yumeng Yuan, Shoumian Chen, Zhidong Tang, Xufeng Kou, Qiming Shao, Chengwei Cao, Ao Guo, Shaojian Hu, Yuhang Zhao
Publikováno v:
IEEE Electron Device Letters. 41:661-664
This paper presents experimental characterizations and device modeling on the nanoscale MOSFETs with 40 nm low-power CMOS technology. Systematic temperature-dependent ${I}_{D}$ - ${V}_{GS}$ results of NMOS/PMOS devices reveal that both the threshold
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::854f16063a73605143bc162530bbd555
https://doi.org/10.1109/led.2020.2984280
https://doi.org/10.1109/led.2020.2984280