Zobrazeno 1 - 10
of 47
pro vyhledávání: '"Shoji Shukuri"'
Publikováno v:
IEEE Transactions on Electron Devices. 49:1302-1307
For pt. I see ibid., vol. 49, no. 7, pp. 1302-1307 (2002). In this work, we demonstrate the feasibility of using channel initiated secondary electron (CHISEL) programming in high density flash memories containing fully scaled memory cells. We discuss
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a539e61862a808b7e2ebb8d111835e8c
https://doi.org/10.1109/ted.2002.1013290
https://doi.org/10.1109/ted.2002.1013290
Autor:
Masaaki Mihara, Yoshiki Kawajiri, K. Kobayashi, Taku Ogura, Moriyoshi Nakashima, N. Ajika, Shoji Shukuri, S. Shimizu, H. Otoi
Publikováno v:
2014 IEEE 6th International Memory Workshop (IMW).
This paper describes a byte alterable EEPROM with B4-HE (Back-Bias assisted Band-to-Band tunneling Hot-Electron injection) architecture employing three-transistor of AND-type unit cell for disturb-free operation. B4-EEPROM cell array has been fabrica
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0b83d30120a038f6910ecc298502c053
https://doi.org/10.1109/imw.2014.6849386
https://doi.org/10.1109/imw.2014.6849386
Publikováno v:
IEEE Transactions on Electron Devices. 41:926-931
A new semi-static complementary gain cell for future low power DRAM's has been proposed and experimentally demonstrated. This gain cell consists of a write-transistor and its opposite conduction type read-transistor with a heating gate as a storage n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9f122625245a3e5b278ad664b05bb0f6
https://doi.org/10.1109/16.293303
https://doi.org/10.1109/16.293303
Autor:
Takashi Nishida, Ryo Nagai, Toshikazu Tachibana, Shoji Shukuri, Mayu Aoki, Takesada Akiba, Tokuo Kure, T. Sakai, Yuzuru Ohji, Hiroki Yamashita, Takayuki Kawahara, Goro Kitsukawa, Norio Hasegawa, Yasushi Kawase, T. Kisu, Kazuhiko Sagara, Masashi Horiguchi, Yoshiki Kawajiri, Natsuki Yokoyama
Publikováno v:
IEEE Journal of Solid-State Circuits. 28:1105-1113
256-Mb DRAM circuit technologies characterized by low power and high fabrication yield for file applications are described. The newly proposed and developed circuits are a self-reverse-biasing circuit for word drivers and decoders to suppress the sub
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a9d73d021ef7a93733c52392d287555d
https://doi.org/10.1109/4.245589
https://doi.org/10.1109/4.245589
Autor:
Mitsuo Asai, Takehisa Hayashi, Kenichi Ishibashi, Shoji Shukuri, Suzuki Makoto, Toshio Doi, A. Watanabe
Publikováno v:
IEEE Journal of Solid-State Circuits. 25:403-409
The shielded dynamic complex-gate (SDC) cell is a cell-based design methodology for generating high-speed modules or macrocells using precharged circuit technology. In order to achieve ultrafast operation, a BiCMOS precharged circuit has been develop
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e472e7a12ccb969267dddbabf54bec57
https://doi.org/10.1109/4.52163
https://doi.org/10.1109/4.52163
Publikováno v:
IndraStra Global.
The impact of technological parameter (channel doping, source/drain junction depth) variation and channel length scaling on the reliability of NOR flash EEPROM cells under channel initiated secondary electron (CHISEL) programming is studied. The best
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2b22b1099245755b2e08eb45d739a287
https://igi.indrastra.com/items/show/47799
https://igi.indrastra.com/items/show/47799
Publikováno v:
IndraStra Global.
The origin of drain disturb in NOR Flash EEPROM cells under channel initiated secondary electron (CHISEL) programming operation is identified. A comparative study of drain disturb under channel hot electron (CHE) and CHISEL operation is performed as
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::41ad4696c5096641ab985a7856c9530f
Autor:
H. Yamashita, Tokuo Kure, J. Yugami, Kazuhiko Sagara, H. Shinriki, Norio Hasegawa, Eiji Takeda, H. Goto, Shoji Shukuri
Publikováno v:
1992 Symposium on VLSI Technology Digest of Technical Papers.
A recessed stacked capacitor (RSTC) structure to achieve both fine-pattern delineation and high cell capacitance is presented. Using a RSTC structure, an experimental memory array with 0.25 mu m phase-shift lithography and CVD-W plate technology has
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4c9ea551bebea7d811ea523d7f0ba3fb
https://doi.org/10.1109/vlsit.1992.200618
https://doi.org/10.1109/vlsit.1992.200618
Autor:
Shoji Shukuri, Takashi Nishida, Kazuo Yano, Tadahiko Nishimukai, Makoto Hanawa, Mitsuru Hiraki, Osamu Nishii, Suzuki Makoto
Publikováno v:
1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
A 1000 MIPS computer, integrated on a single chip and experimentally developed using 0.3- mu m self-aligned BiCMOS technology, is described. It features superscalar processing and pipelined access of interleaved secondary cache. The authors describe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a71f710d8a712dd777780278c03ede0a
https://doi.org/10.1109/isscc.1992.200438
https://doi.org/10.1109/isscc.1992.200438
Publikováno v:
Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6e10d137f1a39dc5407b3e8ab0dadacf
https://doi.org/10.7567/ssdm.2003.p10-3
https://doi.org/10.7567/ssdm.2003.p10-3