Zobrazeno 1 - 10
of 24
pro vyhledávání: '"Shiro Sakiyama"'
Autor:
Takashi Morie, Kazuo Matsukawa, Takeshi Okumoto, Shiro Sakiyama, Koji Obata, Takuji Miki, Yoji Bando, Shiro Dosho
Publikováno v:
IEEE Journal of Solid-State Circuits. 50(6):1372-1381
This paper presents a SAR ADC with 71 dB SNDR and 85 dB SFDR at 50 MS/s while keeping low power consumption of 4.2 mW. To achieve high resolution without large increase of power, several SNR and SFDR enhancement techniques are proposed. Firstly, the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5756d4491737c6c8228a2bb40f5613ad
http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100801107
http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100801107
A Low Distortion 3rd-Order Continuous-Time Delta-Sigma Modulator for a Worldwide Digital TV-Receiver
Autor:
Shiro Sakiyama, Masao Takayama, Shiro Dosho, Yosuke Mitani, Yusuke Tokunaga, Koji Obata, Kazuo Matsukawa
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :471-478
This paper presents a low distortion 3rd-order continuous-time delta-sigma modulator for a worldwide digital TV-receiver whose peak SNDR is 69.8dB and SNR is 70.2dB under 1V power supply. To enhance SNDR performance, the mechanisms to occur harmonic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4cb8d072eb9bd1cdc02c8ca8d7311a52
https://doi.org/10.1587/transfun.e95.a.471
https://doi.org/10.1587/transfun.e95.a.471
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:831-843
A practical method for coupled oscillator design is elaborated. The topology analysis of a coupled oscillator, the ways of simulating its sensitivity, initializing its operation, and the oscillation frequency enhancement with nMOS phase couplers are
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dbdd6dd4383a8007bd18536fcab2aa46
https://doi.org/10.1109/jssc.2008.917567
https://doi.org/10.1109/jssc.2008.917567
Autor:
Shiro Sakiyama, T. Okumoto, Y. Bando, Takashi Morie, Shiro Dosho, Koji Obata, Takuji Miki, Kazuo Matsukawa
Publikováno v:
ISSCC
SAR-ADC power efficiency has improved due to its digitally oriented nature that utilizes the high switching speed of nanometer CMOS processes. In recent reports, time-interleaving techniques and multi-bit-per-cycle conversion have boosted speed to th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5e1454b98101cd2761d9c0c29de4e484
https://doi.org/10.1109/isscc.2013.6487731
https://doi.org/10.1109/isscc.2013.6487731
Autor:
Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Shiro Dosho, Kazuo Matsukawa, Koji Obata, Yusuke Tokunaga
Publikováno v:
CICC
This paper presents a 3rd-order continuous time delta-sigma modulator for a worldwide digital TV-receiver whose SNDR is 69.8 dB. An ultimate low power tuning system using RC-relaxation oscillator is developed in order to achieve high yield against PV
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::698b1eb20b9674e1efe730e070c6ab00
https://doi.org/10.1109/cicc.2010.5617591
https://doi.org/10.1109/cicc.2010.5617591
Publikováno v:
2010 Symposium on VLSI Circuits.
This paper describes the first achievement of over 20,000 quality factors among on-chip relaxation oscillators. The proposed Power Averaging Feedback with a Chopped Amplifier enables such a high Q which is close to MEMS oscillators. 1/f noise free de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ffe1298250d7a3d4bdd2a5f833d67e87
https://doi.org/10.1109/vlsic.2010.5560332
https://doi.org/10.1109/vlsic.2010.5560332
Publikováno v:
ISSCC
Recently, on-chip reference oscillators are required for low-cost single-chip applications including biomedical sensors, microcomputers, high-speed interfaces such as DDR I/F and HDMI (for initial negotiation), and SoCs. RC oscillators (including rel
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::76156c6cf0a555c3e17f18a8e0ec2aa9
https://doi.org/10.1109/isscc.2009.4977479
https://doi.org/10.1109/isscc.2009.4977479
Autor:
null Kazuo Matsukawa, null Takashi Morie, null Yusuke Tokunaga, null Shiro Sakiyama, null Yosuke Mitani, null Masao Takayama, null Takuji Miki, null Akinori Matsumoto, null Koji Obata, null Shiro Dosho
Publikováno v:
2009 Asia and South Pacific Design Automation Conference.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd16a94b208a8c5fb557aacd74b65fa6
https://doi.org/10.1109/aspdac.2009.4796560
https://doi.org/10.1109/aspdac.2009.4796560
Publikováno v:
IEEE Journal of Solid-State Circuits. 25:1476-1483
A digital image signal multiprocessor (ISMP), a multiprocessor version of a previous real-time image signal processor (RISP) for gray-level image processing, is discussed. It is composed of a main controller and four processor elements (PEs), which a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0d9efd85bd9147a5945212b05182cc38
https://doi.org/10.1109/4.62183
https://doi.org/10.1109/4.62183
Publikováno v:
ISSCC
A duty-cycle-correcting false-lock-free DLL for DDR interface is proposed. A fully balanced charge-pump equalizes the charge and discharge pulses of the phase detector to reduce update noise. The DLL achieved 49% to 51% duty-cycle output from a 30% t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::13a73c1c992d5382e8e3fa5178903a51
https://doi.org/10.1109/isscc.2006.1696176
https://doi.org/10.1109/isscc.2006.1696176