Zobrazeno 1 - 10 of 39 pro vyhledávání: '"Shinji Miyano"'
1
A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy
Autor: Kousuke Miyaji, Ken Takeuchi, Toshikazu Suzuki, Shinji Miyano
Publikováno v: IEEE Journal of Solid-State Circuits. 48:2239-2249
A post-process carrier injection scheme for 6T-SRAM is proposed. The proposed scheme pinpoints and simultaneously repairs only cells that have low read disturb margin by injecting electrons to the strong pass gate transistor. Compared with the conven
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5da88bfc008e1bf893c35dc30d404cc9
https://doi.org/10.1109/jssc.2013.2262735
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2
Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges
Autor: Atsushi Kawasumi, Y. Yamamoto, Shinji Miyano, S. Moriwaki, Toshikazu Suzuki, Hirofumi Shinohara, Takeshi Sakurai
Publikováno v: IEEE Journal of Solid-State Circuits. 48:924-931
Low voltage SRAM at a near-threshold voltage has two major sources of power waste: excess bit line swing due to the random variation of transistors and dynamic power consumption of the bit line swing of non-selected columns. In order to overcome thes
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::3b6b0f6481320cc569b2436e15526aef
https://doi.org/10.1109/jssc.2012.2237572
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4
Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress
Autor: Takuya Saraya, Anil Kumar, Shinji Miyano, Toshiro Hiramoto
Publikováno v: IEICE Transactions on Electronics. :759-765
The self-improvement of static random access memory (SRAM) cell stability by post-fabrication high-voltage stress is experimentally demonstrated and its mechanism is analyzed using 4k device-matrixarray (DMA) SRAM test element group (TEG). It is show
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5494cbd2ef6487134cd702002ec46561
https://doi.org/10.1587/transele.e96.c.759
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5
Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM
Autor: Ken Takeuchi, Kousuke Miyaji, Shinji Miyano, Yasuhiro Shinozuka
Publikováno v: IEEE Transactions on Circuits and Systems I: Regular Papers. 59:1635-1643
A statistical threshold voltage VTH shift variation of the pass gate (PG) transistor in local electron injected asymmetric PG transistor 6T-SRAM is investigated. Measurements show that the positive correlation between the PG transistor VTH shift (VTH
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5e4c7bd498a396ede9e59a971fb5e333
https://doi.org/10.1109/tcsi.2012.2206504
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6
A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique
Autor: Toshikazu Suzuki, Shusuke Yoshimoto, Shinji Miyano, Masahiko Yoshimoto, Shunsuke Okumura, Masaharu Terada, Hiroshi Kawaguchi
Publikováno v: IEICE Electronics Express. 9(12):1023-1029
This paper introduces a novel half-select resilient dual write wordline 8T (DW8T) SRAM with a sequential writing technique. The dual write wordlines are sequentially activated in a write cycle, and its combination with the half-VDD precharge suppress
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::460eec774340a451a233217e806381c4
https://hdl.handle.net/20.500.14094/90002977
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7
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme
Autor: Masahiko Yoshimoto, Shunsuke Okumura, Shinji Miyano, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masaharu Terada, Toshikazu Suzuki
Publikováno v: IEICE Transactions on Electronics. 95(4):572-578
This paper presents a novel disturb mitigation scheme which achieves low-energy operation for a deep sub-micron 8T SRAM macro. The classic write-back scheme with a dedicated read port overcame both half-select and read-disturb problems. Moreover, it
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::23150a53a773059006120cb70ff238ae
https://hdl.handle.net/20.500.14094/90002972
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8
Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor
Autor: Ken Takeuchi, Shinji Miyano, Shuhei Tanakamaru, Kentaro Honda, Kousuke Miyaji
Publikováno v: IEICE Transactions on Electronics. :564-571
Three types of electron injection scheme: both side injection scheme and self-repair one side injection scheme Type A (injection for once) and Type B (injection for twice) are proposed and analyzed comprehensively for 65nm technology node 6T- and 8T-
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a9d8f8c6699652a0457c98c2b95671cc
https://doi.org/10.1587/transele.e95.c.564
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10
13.4 A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current
Autor: Shinji Miyano, Koji Kohara, Ichiro Wakiyama, Toshiaki Dozaka, Takehiko Hojo, Tsuyoshi Midorikawa, Toshikazu Fukuda, Kenji Hashimoto, Y. Takeyama
Publikováno v: ISSCC
Battery lifetime is the key feature in the growing markets of sensor networks and energy-management system (EMS). Low-power MCUs are widely used in these systems. For these applications, standby power, as well as active power, is important contributo
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::eceb821175a4f85ac0e3c5bc4ed03c62
https://doi.org/10.1109/isscc.2014.6757415
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