Zobrazeno 1 - 10
of 33
pro vyhledávání: '"Shinichiro Shiratake"'
Publikováno v:
ISSCC
A 3D NAND flash memory continues to increase in bit density and performance for both local and cloud data storage applications. The number of WL layers increases to more than 170 layers, up from 96-128 layers presented previously at ISSCC. A floorpla
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::daa74725e79f065c5fce84ef5fb4dc15
https://doi.org/10.1109/isscc42613.2021.9365847
https://doi.org/10.1109/isscc42613.2021.9365847
Publikováno v:
ISSCC
Advancements in embedded memories continue to enable improvements in system designs spanning from automotive to high-performance computing markets. SRAM continues to be a critical technology enabler across the full spectrum of the semiconductor indus
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3d59cbe213b3f0d3e0f70a9176031e67
https://doi.org/10.1109/isscc42613.2021.9365820
https://doi.org/10.1109/isscc42613.2021.9365820
Autor:
Jonathan Chang, Debbie Marr, Ken Takeuchi, Samuel D. Naffziger, Shinichiro Shiratake, Thomas Burd, Henk Corporaal, Naresh R. Shanbhag, Eric Karl, Hugh Mair
Publikováno v:
ISSCC
General-purpose computing has derived performance gains from clock frequency and instructions-per-clock for over four decades; achieving an impressive ∼105 performance increase over the same timeframe. With the future of the traditional computing r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9944df1b606de6c23c308ae741fed9c7
https://doi.org/10.1109/isscc42613.2021.9366007
https://doi.org/10.1109/isscc42613.2021.9366007
Autor:
Vivek De, Shinichiro Shiratake, Dennis Sylvester, Jun Deguchi, Ingrid Verbauwhede, James Myers
Publikováno v:
ISSCC
Energy efficiency as well as security of ubiquitous smart, secure & connected devices at the edge nodes of IoT are critical for realizing robust and intelligent end-to-end cyberphysical systems that deliver compelling new experiences and capabilities
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e90cb62948b03d62ce0b4016f63ced9a
https://doi.org/10.1109/isscc.2018.8310403
https://doi.org/10.1109/isscc.2018.8310403
Publikováno v:
ISSCC
Speed and power are major concerns in today's memory designs, and they are becoming particularly important with the emergence of high-performance computing and deep-learning applications.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5aa268c46804c86c1398dd07ab321aa8
https://doi.org/10.1109/isscc.2018.8310391
https://doi.org/10.1109/isscc.2018.8310391
Autor:
Shinichiro Shiratake, Ryu Ogiwara, Ryousuke Takizawa, Hidehiro Shiga, Sumiko Doumae, Daisaburo Takashima
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:1324-1331
This paper presents highly reliable reference bitline bias designs for 64 Mb and 128 Mb chain FeRAM™. The hysteresis shape deformation of ferroelectric capacitor due to temperature variation causes cell signal level shifts of both “1” and “0
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9a36318df5606f4a8053b02f3fbddd18
https://doi.org/10.1109/jssc.2015.2405932
https://doi.org/10.1109/jssc.2015.2405932
Autor:
Shinichiro Shiratake, Jun Deguchi, Marian Verhelst, Masato Motomura, Meng-Fan Chang, Vivek De
Publikováno v:
ISSCC
This forum brings together experts in software applications, system architectures, and chip designs to explore cognitive computing approaches over the near-, mid-, and long-term.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f0122ae0c6d468e18e94144bc1bdb258
https://doi.org/10.1109/isscc.2017.7870481
https://doi.org/10.1109/isscc.2017.7870481
Autor:
Shuso Fujii, Daisaburo Takashima, Ryu Ogiwara, Daisuke Hashimoto, Akihiro Nitayama, Shinichiro Shiratake, Ryo Fukuda, Susumu Shuto, Yohji Watanabe, Hidehiro Shiga, Tohru Ozaki, Katsuhiko Hoya, Iwao Kunishima, Tadashi Miyakawa, Sumiko Doumae, Takeshi Hamamoto, Hiroyuki Kanaya, Ryosuke Takizawa, Koji Yamakawa
Publikováno v:
ISSCC
A ferroelectric capacitor overdrive technique with shield-bitline drive has been demonstrated and verified by a 130 nm 576 Kb test chip with a 0.7191 μm2 cell. First, cell signal degradation and bitline-to-bitline coupling noise worsened by wide cel
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5daa454ca9ff7463fb3e94791bd14491
https://doi.org/10.1109/jssc.2011.2159053
https://doi.org/10.1109/jssc.2011.2159053
Autor:
Shinichiro Shiratake, Yoshinori Kumura, S. Ohtsuki, Hitoshi Shiga, Sumiko Doumae, Iwao Kunishima, T. Ozaki, Daisaburo Takashima, Tadashi Miyakawa, Ryu Ogiwara, Akihiro Nitayama, Koji Yamakawa, Katsuhiko Hoya, Syuso Fujii, Susumu Shuto
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18:1745-1752
A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a05654e47ec1032b385902092e35fa7e
https://doi.org/10.1109/tvlsi.2009.2034380
https://doi.org/10.1109/tvlsi.2009.2034380
Autor:
Daisuke Hashimoto, Akihiro Nitayama, Daisaburo Takashima, Takeshi Hioka, Yoshiro Shimojo, Hidehiro Shiga, Yuki Yamada, Koji Yamakawa, Katsuhiko Hoya, Toyoki Taguchi, Shoichi Shimizu, Ryu Ogiwara, Hisaaki Nishimura, Tohru Ozaki, Yohji Watanabe, Shinichiro Shiratake, Sumiko Doumae, Iwao Kunishima, Tohru Furuyama, Tadashi Miyakawa, Hiroyuki Kanaya, Souichi Yamazaki, Shuso Fujii, Fumiyoshi Matsuoka, Yasushi Nagadomi, Ryo Fukuda, Ryosuke Takizawa, Yoshinori Kumura, Mitsumo Kawano, Susumu Shuto, Takeshi Hamamoto, Yoshihiro Minami, Kosuke Hatsuda
Publikováno v:
ISSCC
An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1fda70ed57de6c8e43a679a78faba8b0
https://doi.org/10.1109/jssc.2009.2034414
https://doi.org/10.1109/jssc.2009.2034414