Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Shinichi Domae"'
Publikováno v:
Journal of Electrical Engineering & Technology. 18:367-376
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::54a24864ab827b27133536272e493470
https://doi.org/10.1007/s42835-022-01255-4
https://doi.org/10.1007/s42835-022-01255-4
Publikováno v:
2021 24th International Conference on Electrical Machines and Systems (ICEMS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eaf58309603781ebeeb410efae7deea8
https://doi.org/10.23919/icems52562.2021.9634427
https://doi.org/10.23919/icems52562.2021.9634427
Publikováno v:
Microelectronics Reliability. 39:507-513
The stress-induced voiding (SV) in Al-alloy films with stacked tungsten via structures was investigated. Voids were found in interconnections with stacked and borderless vias that had resistance increase after the aging tests. Failure occurs most fre
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0f0ac633038810342e4450b5dfe526b8
https://doi.org/10.1016/s0026-2714(99)00015-3
https://doi.org/10.1016/s0026-2714(99)00015-3
Autor:
D. Perry, Alex Yakovlev, Pol Marchal, Geert Van der Plas, Shinichi Domae, Panagiotis Asimakopoulos, Jonghoon Cho, N. Minas
Publikováno v:
2011 IEEE ICMTS International Conference on Microelectronic Test Structures.
We present a test structure to measure the impact of 3D processing, especially through silicon vias, on FET devices. We also show proven techniques for enabling large numbers of devices to be accessed from a limited number of pads. We will show that
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::207ec7adb3edd5bcf7562395394f972f
https://doi.org/10.1109/icmts.2011.5976872
https://doi.org/10.1109/icmts.2011.5976872
Autor:
G. Van der Plas, Victor Moroz, Abdelkarim Mercha, Chukwudi Okoro, Serge Biesemans, J.H. Cho, Philippe Soussan, P. Asimakopoulos, Alex Yakovlev, I. De Wolf, J. Van Olmen, Y. Yang, Eric Beyne, Shinichi Domae, Bart Swinnen, Pol Marchal, Sarasvathi Thangaraju, Munkang Choi, Youssef Travaly, D. Sabuncuoglu Tezcan, N. Minas, D. Perry, Augusto Redolfi
Publikováno v:
2010 International Electron Devices Meeting.
As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::befe3dc00aa843a5b85bd2de047fdbf1
https://doi.org/10.1109/iedm.2010.5703278
https://doi.org/10.1109/iedm.2010.5703278
Autor:
D. Perry, Patrick Jaenen, Silvia Armini, G. Katti, Harold Philipsen, Youssef Travaly, Erik Sleeckx, D. Sabuncuoglu Tezcan, Nancy Heylen, I. Debusschere, N. Minas, G. Van der Plas, Y. Yang, Wouter Ruythooren, Serge Biesemans, P. Asimakopoulos, Chukwudi Okoro, Ming Zhao, Aleksandar Radisic, I. De Wolf, Anne Jourdain, P. Marchal, S. Thangaraju, J. Van Olmen, Philippe Soussan, E. Rohr, Augusto Redolfi, Riet Labie, Abdelkarim Mercha, M. Kostermans, Bart Swinnen, Tom Schram, T. Chiarella, Jun-Seok Cho, Eric Beyne, Shinichi Domae, A. Van Ammel, Dimitrios Velenis, Michele Stucchi
Publikováno v:
2010 Symposium on VLSI Technology.
3D integration has the potential to alleviate the performance limitations that CMOS scaling is facing provided that it preserves the integrity of both front end and back end devices and constituting materials. The impact of wafer thinning and of the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e7dcc88badf75de17deb4dab1cf7b857
https://doi.org/10.1109/vlsit.2010.5556190
https://doi.org/10.1109/vlsit.2010.5556190
Conference
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