Výsledky vyhledávání - "Shinichi Domae"

Stress-induced voiding in stacked tungsten via structure

Autor: Shinichi Domae, Keiji Okuma, Ryuji Eto

Publikováno v: Microelectronics Reliability. 39:507-513

The stress-induced voiding (SV) in Al-alloy films with stacked tungsten via structures was investigated. Voids were found in interconnections with stacked and borderless vias that had resistance increase after the aging tests. Failure occurs most fre

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0f0ac633038810342e4450b5dfe526b8
https://doi.org/10.1016/s0026-2714(99)00015-3

Zobrazit plný text záznamu

An efficient array structure to characterize the impact of through silicon vias on FET devices

Autor: D. Perry, Alex Yakovlev, Pol Marchal, Geert Van der Plas, Shinichi Domae, Panagiotis Asimakopoulos, Jonghoon Cho, N. Minas

Publikováno v: 2011 IEEE ICMTS International Conference on Microelectronic Test Structures.

We present a test structure to measure the impact of 3D processing, especially through silicon vias, on FET devices. We also show proven techniques for enabling large numbers of devices to be accessed from a limited number of pads. We will show that

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::207ec7adb3edd5bcf7562395394f972f
https://doi.org/10.1109/icmts.2011.5976872

Zobrazit plný text záznamu

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

Publikováno v: 2010 International Electron Devices Meeting.

As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key co

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::befe3dc00aa843a5b85bd2de047fdbf1
https://doi.org/10.1109/iedm.2010.5703278

Zobrazit plný text záznamu

Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

Publikováno v: 2010 Symposium on VLSI Technology.

3D integration has the potential to alleviate the performance limitations that CMOS scaling is facing provided that it preserves the integrity of both front end and back end devices and constituting materials. The impact of wafer thinning and of the

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e7dcc88badf75de17deb4dab1cf7b857
https://doi.org/10.1109/vlsit.2010.5556190

Zobrazit plný text záznamu