Zobrazeno 1 - 10
of 60
pro vyhledávání: '"Shin-puu Jeng"'
Autor:
Shin-Puu Jeng, Monsen Liu
Publikováno v:
2022 International Electron Devices Meeting (IEDM).
Publikováno v:
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).
Autor:
Shin-Puu Jeng, Ming-Chih Yew, Ching-Fang Chen, Cheng-Hsiang Hsieh, Po-Yao Lin, Shu-Shen Yeh, H. K. Cheng, Szu-Ying Chen, Y. J. Lu, Lin Chia-Hsiang, Chuang Po-Yao
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
Organic interposer (CoWoS®-R) is one of the most promising heterogeneous integration platform solutions for high-speed and artificial intelligence applications. Components such as chiplets, high-bandwidth memory, and passives can be integrated into
Autor:
Jin-Hua Wang, Y. C. Lee, Po-Chen Lai, S. K. Cheng, Y. S. Lin, Chia-Kuei Hsu, Shu-Shen Yeh, Po-Yao Lin, Ming-Chih Yew, C. H. Chen, Shin-Puu Jeng
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
In order to ensure good performance and long-term reliability of fan-out package, the interfacial strength of Underfill (UF) and polymer (PM) lamination plays an important role because of physical strength and electrical requirement. Accordingly, the
Autor:
Shin-Puu Jeng, Po-Chen Lai, L. L. Liao, Jin-Hua Wang, Po-Yao Lin, Shu-Shen Yeh, Chia-Kuei Hsu, Ming-Chih Yew, Y. S. Lin, S. K. Cheng, T. Y. Lee, C. H. Chen
Publikováno v:
2020 15th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).
Underfill (UF) polymer (PM) structures are becoming increasingly popular in fan-out packages because they exhibit several advantages, such as protection from mechanical stress and package- to-system electrical and thermal conductivity. The laminate i
Autor:
Po-Yao Chuang, Shin-Puu Jeng, L.-L Liao, Wu Yi-Wen, Szu-Ying Chen, Chia-Kuei Hsu, Hung Shih-Ting, Lin Meng-Liang, Ming-Chih Yew, Tsai Po-Hao, D.-C. Wong, S. K. Cheng, P.-Y. Lai
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
A new ultra-thin high-density hybrid package that combines fan-out RDL with a backside laminated interposer is developed for mobile applications. The package features up to six fan-out RDL layers for chiplet integration and two to four routing layers
Autor:
Po-Chen Lai, Chia-Kuei Hsu, Shu-Shen Yeh, Kuang-Chun Lee, Shin-Puu Jeng, Che-Chia Yang, S. K. Cheng, Jin-Hua Wang, Po-Yao Lin, Dion Tseng, Ming-Chih Yew
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
Fan-out wafer level package (FOWLP) is a disruptive technology in the semiconductor packaging industry. Demand for higher system performance has caused an increase in both package size and the complexity of heterogeneous integration. Large warpage, w
Autor:
Kuang-Chun Lee, Po-Chen Lai, Chia-Kuei Hsu, Shu-Shen Yeh, Wen-Yi Lin, Ming-Chih Yew, Jin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng, Che-Chia Yang
Publikováno v:
2019 IEEE 69th Electronic Components and Technology Conference (ECTC).
Board level reliability during drop impact is a major concern for electronic packages. The impact force generated as the casing strikes the ground can cause electronic device failures in handheld products. The full drop testing procedure is costly an
Autor:
Po-Chen Lai, Jin-Hua Wang, Ming-Chih Yew, Po-Yao Lin, Shin-Puu Jeng, Li-Ling Liao, Yu-Sheng Lin, Che-Chia Yang, Chia-Kuei Hsu, Kuang-Chun Lee, Shu-Shen Yeh, Wen-Yi Lin
Publikováno v:
2018 13th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).
Warpage has always been an important issue in electronic packaging, especially for fan-out and flip-chip chip scale packages (fcCSP). The molded underfill for encapsulation plays a key role in warpage control. It is critical to establish a fundamenta
Autor:
Po-Chen Lai, Shin-Puu Jeng, Che-Chia Yang, Po-Yao Lin, Wen-Yi Lin, Chia-Kuei Hsu, Jin-Hua Wang, Shu-Shen Yeh, Kuang-Chun Lee, Ming-Chih Yew
Publikováno v:
2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
The molded underfill (MUF) offers many unique advantages, including lower material costs, higher throughput, and excellent reliability for flip-chip chip scale packages (fcCSP) and fan-out packages. The assembly process yield and reliability of these