Výsledky vyhledávání - "Shin-Deok Kang"

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS

Publikováno v: ISSCC

As the speed of DRAM increases and the applications spread, DLLs for DRAM require low-jitter characteristics as well as wide operating range in frequency and voltage domains. Even though digital DLLs have improved jitter control schemes [1,2,4], it i

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d3e2e286b65c62e3836c96bc0c173b61
https://doi.org/10.1109/isscc.2009.4977347

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A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

Publikováno v: ISSCC

We design a DLL that has a slew-rate controlled duty-cycle-correction (DCC) with a fully digital controlled duty-cycle-error detector and has the update gear circuit to shift update mode for low power consumption. The DLL is composed of a dual loop a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::4b6e0d0fb4f9670bb5ee6c1eea2be2c2
https://doi.org/10.1109/isscc.2008.4523167

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Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface

Autor: Ye Seok Yang, Dong Uk Lee, Jung-Woo Lee, Shin Deok Kang, Young Jung Choi, Hyun-woo Lee, Kwan-Weon Kim, Sang-hoon Shin, Young Kyoung Choi, Nak Kyu Park, Won-Joo Yun, Hyeong Ouk Lee, Seung Wook Kwack

Publikováno v: ISSCC

In this work, a multi-slew-rate output driver is developed to cope with the supply voltage variation and the different I/O component capacitance (denoted by CIO) condition. For accurate data transfer, it is necessary to reduce the design loss in the

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a44c495b7d801bb6c899f6bd914cc964
https://doi.org/10.1109/isscc.2008.4523166

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A Low Power Digital DLL with Wide Locking Range for 3Gbps 512Mb GDDR3 SDRAM

Publikováno v: 2006 IEEE Asian Solid-State Circuits Conference.

A new low power, low cost and high performance register-controlled digital delay locked loop with wide locking range is presented. The DLL has dual loops with single replica block, duty cycle correction enhance controller (DCCEC), smart power down co

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6ce5ff40096b319a115e06fb9c94ea05
https://doi.org/10.1109/asscc.2006.357916

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Conference

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.

Publikováno v: 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers; 2008, p282-613, 332p

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Conference

Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface.

Autor: Dong Uk Lee, Shin Deok Kang, Nak Kyu Park, Hyun Woo Lee, Young Kyoung Choi, Jung Woo Lee, Seung Wook Kwack, Hyeong Ouk Lee, Won Joo Yun, Sang Hoon Shin, Kwan Weon Kim, Young Jung Choi, Ye Seok Yang

Publikováno v: 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers; 2008, p280-613, 334p

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Conference

A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL.

Autor: Dong Uk Lee, Hyun Woo Lee, Ki Chang Kwean, Young Kyoung Choi, Hyong Uk Moon, Seung Wook Kwack, Shin Deok Kang, Kwan Weon Kim, Yong Ju Kim, Young Jung Choi, Moran, P., Jin Hong Ahn, Joong Sik Kih

Publikováno v: 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers; 2006, p547-556, 10p

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Conference

A Low Power Digital DLL with Wide Locking Range for 3Gbps 512Mb GDDR3 SDRAM.

Publikováno v: 2006 IEEE Asian Solid-State Circuits Conference; 2006, p323-326, 4p

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Conference

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS.

Publikováno v: 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers; 2009, p140-141a, 3p

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