Zobrazeno 1 - 10
of 23
pro vyhledávání: '"Shin'ichiro Okazaki"'
Publikováno v:
IPSJ Transactions on System LSI Design Methodology. 3:47-56
We have developed an “XC core” processor that achieves low cost, high performance, and low power consumption through the use of a highly parallel SIMD architecture (the SIMD mode), as well as achieves high flexibility by morphing into a MIMD arch
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::06d7aead90c8441f5c05582be1fa173d
https://doi.org/10.2197/ipsjtsldm.3.47
https://doi.org/10.2197/ipsjtsldm.3.47
Autor:
Shorin Kyo, Shin'ichiro Okazaki
Publikováno v:
Journal of Signal Processing Systems. 62:5-16
This paper presents IMAPCAR, a 100GOPS programmable highly parallel vision processor LSI consuming less than 2 W of power for in-vehicle vision tasks of driver assistance systems. First, requirements of vision processors for driver assistance systems
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::905f3fb26acc0fd1d762bbe15968b4c7
https://doi.org/10.1007/s11265-008-0297-0
https://doi.org/10.1007/s11265-008-0297-0
Publikováno v:
MVA
This paper describes the real-time implementation of a vision-based overtaking vehicle detection method for driver assistance systems using IMAPCAR, a highly parallel SIMD linear array processor. The implemented overtaking vehicle detection method is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::93732f43fd14daf3ed802c519a531be1
https://doi.org/10.1093/ietisy/e91-d.7.1899
https://doi.org/10.1093/ietisy/e91-d.7.1899
Publikováno v:
ISCA
Embedded processors for video image recognition require to address both the cost (die size and power) versus real-time performance issue, and also to achieve high flexibility due to the immense diversity of recognition targets, situations, and applic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ceb0e3ea0a2eba468274c7e418b3acd7
https://doi.org/10.1145/1080695.1069982
https://doi.org/10.1145/1080695.1069982
Publikováno v:
IEEE Journal of Solid-State Circuits. 38:1992-2000
This paper describes a 51.2-GOPS video recognition processor, which achieves real-time multiple processing of in-vehicle video recognition applications in software, while at the same time satisfying power efficiency requirements of an in-vehicle devi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7818d54b520fde9e7f1af867a5b6136a
https://doi.org/10.1109/jssc.2003.818128
https://doi.org/10.1109/jssc.2003.818128
Publikováno v:
Systems and Computers in Japan. 27:26-36
An integrated memory array processor (IMAP) ULSI with 64 processing elements and a 2 Mb SRAM has been developed to build a compact real-time image processing system. The chip attains a 3.84 GIPS peak performance through the use of SIMD parallel proce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::52fd94ba013fe8402126e904e369d2fe
https://doi.org/10.1002/scj.4690270303
https://doi.org/10.1002/scj.4690270303
Publikováno v:
Journal of the Robotics Society of Japan. 13:339-342
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::db7648dc912257c74c80a05de0a086cd
https://doi.org/10.7210/jrsj.13.339
https://doi.org/10.7210/jrsj.13.339
Publikováno v:
IEEE Transactions on Circuits and Systems for Video Technology. 5:446-452
This paper describes the real-time vision system (RVS-2) which shows quite high performance for low-level image processing while it is implemented in a one-board type compact size format with small power consumption. The RVS-2 consists of an IMAP boa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1a02c51d7e9a6ea471c36db586027fc0
https://doi.org/10.1109/76.473557
https://doi.org/10.1109/76.473557
Publikováno v:
MVA
This paper describes a real-time vision system (RVS) architecture and performance and its use of an integrated memory array processor (IMAP) prototype. This prototype integrates eight 8-bit processors and a 144-kbit SRAM on a single chip. The RVS was
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6759aa82d313fed015971d7fe7308768
https://doi.org/10.1007/bf01213412
https://doi.org/10.1007/bf01213412
Publikováno v:
Journal of Circuits, Systems and Computers. :227-245
This paper presents architectural features and performances for an Integrated Memory Array Processor (IMAP) LSI, which integrates a large capacity memory and a one-dimensional SIMD processor array on a single chip. The IMAP has a conventional memory
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3fcd8113e75db6226348bf3bd51ef4b0
https://doi.org/10.1142/s0218126692000155
https://doi.org/10.1142/s0218126692000155