Zobrazeno 1 - 10
of 176
pro vyhledávání: '"Shih-Lien Lu"'
Publikováno v:
IEEE Access, Vol 9, Pp 109260-109288 (2021)
Polynomial-time attacks designed to run on quantum computers and capable of breaking RSA and AES are already known. It is imperative to develop quantum-resistant algorithms before quantum computers become available. Computationally hard problems defi
Externí odkaz:
https://doaj.org/article/0d1168d6881e411cbf766cfc3ff24aee
Autor:
Shih-Lien Lu
Publikováno v:
2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::91177fb0ac7899bf9616465e38f6a2ad
https://doi.org/10.1109/vlsi-tsa/vlsi-dat57221.2023.10134130
https://doi.org/10.1109/vlsi-tsa/vlsi-dat57221.2023.10134130
Publikováno v:
VLSI-DAT
A physically unclonable function (PUF) targeting internet of things is implemented in 28nm CMOS. By filtering, the reliability of a PUF is improved leading to lower overhead. Measured results show that the proposed design can operate correctly at tem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::38aad9d0dc369279d3fd43ba02513bac
https://doi.org/10.1109/vlsi-dat.2019.8741640
https://doi.org/10.1109/vlsi-dat.2019.8741640
Autor:
Shih-Lien Lu, Yuan-Hsi Chou
Publikováno v:
VLSI-DAT
Advanced Encryption Standard (AES) is a specification for electronic data encryption. This standard has become one of the most widely used encryption method and has been implemented in both software and hardware. AES has excellent resistance against
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f3d3ffb91451bcb8719dd87b464cafb1
https://doi.org/10.1109/vlsi-dat.2019.8741835
https://doi.org/10.1109/vlsi-dat.2019.8741835
Publikováno v:
IEEE Transactions on Computers. 65:108-121
Ever-growing application data footprints demand faster main memory with larger capacity. DRAM has been the technology choice for main memory due to its low latency and high density. However, DRAM cells must be refreshed periodically to preserve their
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5c813c9a90c531c9427ab36d9a8c6c13
https://doi.org/10.1109/tc.2015.2417540
https://doi.org/10.1109/tc.2015.2417540
Autor:
Shih-Lien Lu
Publikováno v:
VLSI-DAT
A system is as secure as its weakest link. Current computing systems employ a multiple-layer approach to build a trusted environment. At the bottom of this multi-layer approach is a hardware root of trust which other layers build upon. It is importan
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0d94bd334685567d3b380b2a24917c73
https://doi.org/10.1109/vlsi-dat.2018.8373271
https://doi.org/10.1109/vlsi-dat.2018.8373271
Autor:
Shigeki Tomishima, Yung-Fa Chou, Wang Chun-Kai, Yung-Ching Hsieh, Shih-Lien Lu, Der-Min Yuan, Chi-Kang Chen, Chun-Wei Lo, Ding-Ming Kwai, Zhe Wang, Wei Wu, Jenn-Shiang Lai, Tah-Kang Joseph Ting, Li-Chin Tien, Hsu Wen-Pin, Chun-Peng Wu, Pat Stolt, Gyh-Bin Wang, Ming-Hung Wang, Chien-Chih Huang
Publikováno v:
ISSCC
In recent years, the demand for memory performance has grown rapidly due to the increasing number of cores on a single CPU, along with the integration of graphics processing units and other accelerators. Caching has been a very effective way to relie
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aad31c0ef6fea55b2452c143e4569533
https://doi.org/10.1109/isscc.2017.7870432
https://doi.org/10.1109/isscc.2017.7870432
Autor:
Andre Schaefer, Jen-Chieh Yeh, Cheng-Wen Wu, Shih Lien Lu, Pei-Wen Luo, Hsiu Chuan Shih, Shu-Yen Lin, Ding-Ming Kwai
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 33:1356-1369
DRAM renovation calls for a holistic architecture exploration to cope with bandwidth growth and latency reduction need. In this paper, we present DRAM area power timing (DArT), a DRAM area, power, and timing modeling tool, for array assembly and inte
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d91b89c875fec7f697a90f0f530067a7
https://doi.org/10.1109/tcad.2014.2323203
https://doi.org/10.1109/tcad.2014.2323203
Publikováno v:
IPCCC
Large off-die stacked DRAM caches have been proposed to provide higher effective bandwidth and lower average latency to main memory. Designing a large off-die DRAM cache with conventional block size requires a large tag array which is impractical to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bd1d6571675cce701879c5549fe66b4e
https://doi.org/10.1109/pccc.2016.7820659
https://doi.org/10.1109/pccc.2016.7820659
Publikováno v:
PDCAT
In order to hide long memory latency and alleviate memory bandwidth requirement, a fourth-level cache (L4) is introduced in modern high-performance multi-core systems for supporting parallel computation. However, additional cache level causes higher
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c2649d86e67695d55dbea57d15f412f1
https://doi.org/10.1109/pdcat.2016.017
https://doi.org/10.1109/pdcat.2016.017