Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Shien-Yu Huang"'
Publikováno v:
IEEE Transactions on Consumer Electronics. 56:1837-1842
In this paper, a hybrid parallel motion estimation architecture based on the fast top-winners algorithm is proposed. In the first instance, the fast top-winners search algorithm is discussed based on the pel-subsampling technique to reduce the comput
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::19ca7c9378da986e2b0f547e3aa3e7d6
https://doi.org/10.1109/tce.2010.5606334
https://doi.org/10.1109/tce.2010.5606334
Hardware efficient coarse-to-fine fast algorithm for H.264/AVC variable block size motion estimation
Publikováno v:
ISCAS
In this paper, a hardware efficient coarse-to-fine fast algorithm for H.264 motion estimation is proposed. We present hardware friendly two-step searching flow to obtain the 41 MVs of the variable block size motion estimation (VBSME) efficiently. At
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::22e288fd18844a61e0267479651b4cd9
https://doi.org/10.1109/iscas.2009.5118091
https://doi.org/10.1109/iscas.2009.5118091
Publikováno v:
ICME
In this paper, an algorithm and architecture co-design for parallel motion estimator based on fast pel-subsampling algorithm is proposed. Firstly, we proposed a hard-wareoriented pel-subsampling algorithm to reduce the computational amount of the sum
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f9bfc41bb760c29df001396a2f7bbbca
https://doi.org/10.1109/icme.2008.4607611
https://doi.org/10.1109/icme.2008.4607611
Publikováno v:
2009 IEEE International Symposium on Circuits & Systems; 2009, p1657-1660, 4p
Publikováno v:
2008 IEEE International Conference on Multimedia & Expo; 2008, p1021-1024, 4p