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pro vyhledávání: '"Sheng-Hann Wu"'
Autor:
Sheng-Hann Wu, 吳昇翰
94
A 20-GHz clock multiplication unit for SONET OC-768 systems employs dual loops and third-order loop filter to suppress the jitter. Realized in 0.18-um CMOS technology, this circuit achieves an output jitter of 0.2 ps,rms and 4.5 ps,pp while c
A 20-GHz clock multiplication unit for SONET OC-768 systems employs dual loops and third-order loop filter to suppress the jitter. Realized in 0.18-um CMOS technology, this circuit achieves an output jitter of 0.2 ps,rms and 4.5 ps,pp while c
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/26929541740156984447
Autor:
Sheng-Hann, Wu
Thesis (M.A.)--National Taiwan University Graduate Institute of Electronical Engineering
Includes bibliographical references
Includes bibliographical references