Zobrazeno 1 - 10
of 575
pro vyhledávání: '"Shen-Iuan Liu"'
Autor:
Zhi-Heng Kang, Shen-Iuan Liu
Publikováno v:
IEEE Journal of Solid-State Circuits. 58:806-816
Autor:
Wen-Chi Huang, Shen-Iuan Liu
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 69:4709-4713
Autor:
Yao-Hung Tsai, Shen-Iuan Liu
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 30:905-914
Autor:
Yao-Hung Tsai, Shen-Iuan Liu
Publikováno v:
2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT).
Autor:
Yi-En Hsu, Shen-Iuan Liu
Publikováno v:
2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT).
Autor:
Jia-Rong Chang, Shen-Iuan Liu
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 69:2026-2030
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 69:894-898
A digital clock/data recovery (CDR) circuit with a one-tap speculative decision feedback equalizer (DFE) and a calibration circuit is presented. This CDR circuit is fabricated in 40-nm CMOS technology and its active area is 0.1 mm2. For a channel los
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 69:269-273
A sub-sampling phase-locked loop (SSPLL) with a subsampling delay-locked loop is presented to extend the loop bandwidth and achieve the low jitter. A falling-edge tuning loop is added to align the falling edge of the reference clock with the rising o
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 69:60-64
A wide-range frequency detector (FD) is presented for baud-rate clock and data recovery (CDR) circuits. It achieves a wide frequency capture range, a short lock time, and a low power. By using this FD, a referenceless quarter-rate CDR circuit with a
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 68:4566-4575
A 10.4-16-Gb/s reference-less and baud-rate clock and data recovery (CDR) circuit with a one-tap speculative decision feedback equalizer (DFE) is presented. The quarter-rate CDR circuit uses a pattern-based phase detector (PD) and the proposed FD. Th