Zobrazeno 1 - 10
of 25
pro vyhledávání: '"Sharon Lim Pei Siang"'
Autor:
Vivek Chidambaram, Sharon Lim Pei Siang, Wang Xiangyu, Vasarla Nagendra Sekhar, Surya Bhattacharya
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 7, Pp 1209-1216 (2019)
Achieved system level heterogeneous integration involving 130 nm tech node active Si interposer, two 65 nm tech node I/O chips and one 28 nm tech node FPGA die. Chip on Chip on Substrate packaging methodology was demonstrated for handling active Si i
Externí odkaz:
https://doaj.org/article/8f74a72230314abdb958643a6f01cf44
Autor:
K. B. Zheng, Sun Mei, Sharon Lim Pei Siang, Jong Ming Chinq, Lau Boon Long, Zhou Lin, Lim Teck Guan
Publikováno v:
2022 IEEE 24th Electronics Packaging Technology Conference (EPTC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5355cdd69a12fff497122cb1d4f972c4
https://doi.org/10.1109/eptc56328.2022.10013127
https://doi.org/10.1109/eptc56328.2022.10013127
Autor:
Teyuh Chou, Wei Tang, Mihai D. Rotaru, Chester Liu, Rahul Dutta, Sharon Lim Pei Siang, David Ho Soon Wee, Surya Bhattacharya, Zhengya Zhang
Publikováno v:
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bf915032fa27edcb6f0192a7b3266618
https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830249
https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830249
Autor:
Ser Choong Chong, Ismael Cereno Daniel, Sharon Lim Pei Siang, Joseph Shim Cheng Yi, Alvin Lai Wai Song, Woon Leng Loh
Publikováno v:
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b11601cc52c4f7db4262a0866a97e800
https://doi.org/10.1109/ectc51906.2022.00311
https://doi.org/10.1109/ectc51906.2022.00311
Autor:
Soon Wee Ho, Hsiao Hsiang-Yao, Lau Boon Long, Sharon Lim Pei Siang, Lim Teck Guan, Chai Tai Chong
Publikováno v:
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2af2f31079e9b42f5e7c5d03163b9bb4
https://doi.org/10.1109/ectc51906.2022.00221
https://doi.org/10.1109/ectc51906.2022.00221
Autor:
Sajay Bhuvanendran Nair Gourikutty, Ming Chinq Jong, Chockanathan Vinoth Kanna, David Soon Wee Ho, Seit Wen Wei, Sharon Lim Pei Siang, Jiaqi Wu, Teck Guan Lim, Rathin Mandal, Jason Tsung-Yang Liow, Surya Bhattacharya
Publikováno v:
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::704eecc72e2321a35bc1f1506940f8b9
https://doi.org/10.1109/ectc51906.2022.00074
https://doi.org/10.1109/ectc51906.2022.00074
Publikováno v:
2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eac1b73f080394ec9a1e5676e9d8e55e
https://doi.org/10.1109/eptc53413.2021.9663939
https://doi.org/10.1109/eptc53413.2021.9663939
Autor:
Sharon Lim Pei Siang, Chong Ser Choong, Lim Teck Guan, Han Yong, Surya Bhattacharya, David Ho, Chai Tai Chong
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
High density heterogeneous integration of ASIC and HBM2 through the use of embedded fine pitch interconnect (EFI) in face-to-face configuration using RDL 1st fan-out wafer packaging platform is demonstrated. The EFI configuration, thermal design cons
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b752aaad551fa44e8aba4bbc32f99ef5
https://doi.org/10.1109/ectc32696.2021.00348
https://doi.org/10.1109/ectc32696.2021.00348
Autor:
Salahuddin Raju, Ravinder Pal Singh, Simon Lim Siak Boon, Ho Soon Wee, Sharon Lim Pei Siang, Soh Siew Boon
Publikováno v:
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC).
Fan-out Wafer Level Packaging is widely and commonly adopted to ease implementation for low-cost packaging. It offers an enhanced solution of standard wafer-level packaging (WLP), which gained popularity for its application in embedding integrated ci
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3e317d0e3b101b0e69490407bbe64f1c
https://doi.org/10.1109/eptc50525.2020.9315018
https://doi.org/10.1109/eptc50525.2020.9315018
Publikováno v:
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC).
Current industry trends in the microelectronics packaging is going towards increasing in I/O density and small size packaging. Common use of solder material in packaging are the lead free solders. The popular lead free alloys include the SnAgCu (SAC)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::87c07a044c3c6bfc8769c8010d59afee
https://doi.org/10.1109/eptc50525.2020.9315175
https://doi.org/10.1109/eptc50525.2020.9315175