Zobrazeno 1 - 10
of 23
pro vyhledávání: '"Shaolei Quan"'
Autor:
Lijun Li, K. Ling, Tomasz Prokop, A. Sinha, R. Kothari, Hiroshi Kimura, Eric Zhang, Chaitanya Palusa, Freeman Zhong, Jen Dong, S. Lowrie, G. Hom, Hairong Gao, Tai Jing, Chintan Desai, Cathy Ye Liu, Ram Surya Narayan, Pervez M. Aziz, Wing Liu, M. Garcia, Amaresh V. Malipatil, T. Huynh, Shaolei Quan, A. Rajashekara, C. Zhong
Publikováno v:
ISSCC
A robust transceiver designed for NRZ signaling beyond 10Gb/s over long-range physical media (including electrical backplanes, copper cables and optical modules) must contend with significant challenges from insertion loss, crosstalk, and reflection.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a7f87bed5505299bca326b0eef716c61
https://doi.org/10.1109/jssc.2011.2168871
https://doi.org/10.1109/jssc.2011.2168871
Autor:
Shaolei Quan, Freeman Zhong, Wing Liu, Pervez Aziz, Tai Jing, Jen Dong, Chintan Desai, Hairong Gao, Monica Garcia, Gary Hom, Tony Huynh, Hiroshi Kimura, Ruchi Kothari, Lijun Li, Cathy Liu, Scott Lowrie, Kathy Ling, Amaresh Malipatil, Ram Narayan, Tom Prokop, Chaitanya Palusa, Anil Rajashekara, Ashutosh Sinha, Charlie Zhong, Eric Zhang
Publikováno v:
2011 IEEE International Solid-State Circuits Conference.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e1d6adaaa14ba7193f561eb23dd0bde5
https://doi.org/10.1109/isscc.2011.5746348
https://doi.org/10.1109/isscc.2011.5746348
Publikováno v:
2006 13th IEEE International Conference on Electronics, Circuits & Systems; 2006, p371-374, 4p
Publikováno v:
20th IEEE International Symposium on Defect & Fault Tolerance in VLSI Systems (DFT'05); 2005, p563-572, 10p
Publikováno v:
14th Asian Test Symposium (ATS'05); 2005, p70-75, 6p
Publikováno v:
2005 IEEE International Workshop on Memory Technology, Design & Testing (MTDT'05); 2005, p146-151, 6p
Publikováno v:
ICECS
Gate-oxide defect is the major cause of the reliabliability problems for CMOS ICs. The common practice for reliability enhancement is the use of extreme-voltage screening and then the high-temperature burn-in screening, where the Iddq-test approach i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::52adad09dc096e63e5b38d0e705a924d
https://doi.org/10.1109/icecs.2006.379802
https://doi.org/10.1109/icecs.2006.379802
Publikováno v:
ISCAS (4)
A novel architecture is proposed for a low-power reconfigurable unsigned multiplier with one level of recursion. Compared with the conventional scheme for n/spl times/n-b unsigned multiplication, which employs four n/2/spl times/n/2 non-additive mult
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::36a60de86aa0c2224f63997139309b06
https://doi.org/10.1109/iscas.2005.1465340
https://doi.org/10.1109/iscas.2005.1465340
Publikováno v:
Asian Test Symposium
Previous work on extreme-voltage stress test of analog ICs has suffered either from time-costly circuit-level simulation or from the considerable number of bits in the control signal added to circuit for stress operation. This paper presents several
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::23e6e038f6525cce4373830b04badbb5
https://doi.org/10.1109/ats.2005.49
https://doi.org/10.1109/ats.2005.49
Publikováno v:
ISCAS (2)
A power-optimized 8-bit priority encoder cell that simplifies the conventional circuit from 102 to 62 transistors is presented. A parallel priority look-ahead architecture that reduces the delay time of priority propagation is introduced. The 8-bit P
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dae1c774c550a78bfd01e313b897e17d
https://doi.org/10.1109/iscas.2004.1329381
https://doi.org/10.1109/iscas.2004.1329381