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pro vyhledávání: '"Shaojun Wei Shaojun Wei"'
Publikováno v:
2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03.
With rapid development of technology, interconnect will occupy much chip area and gradually dominate circuit performance, interconnect optimization in high level design become more and more important. In this paper, we formulate an interconnect reuse
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1d24fde7715b7e93e6789dc73279f940
https://doi.org/10.1109/icasic.2003.1277545
https://doi.org/10.1109/icasic.2003.1277545
