Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Shang-Yun Hou"'
Autor:
Shang-yun Hou, 侯尚昀
99
Surveillance systems are to detect if there are people entering, leaving, loitering at the monitored areas. Automatic detection of such events is critical to the early response of security staffs in taking appropriate measures. Traditional su
Surveillance systems are to detect if there are people entering, leaving, loitering at the monitored areas. Automatic detection of such events is critical to the early response of security staffs in taking appropriate measures. Traditional su
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/k2k442
Autor:
Wen-Chih Chiou, Calvin Lu, Douglas Yu, C.H. Tsai, Christine Chiu, C. T. Wang, P. K. Huang, Kai-Yuan Ting, Shang-Yun Hou, W. H. Wei, Clark Hu
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
Chip-on-Wafer-on-Substrate with Si interposer (CoWoS-S) is a TSV-based multi-chip integration technology that is widely used in high performance computing (HPC) and artificial intelligence (AI) accelerator area due to its flexibility to accommodate m
Autor:
Douglas Yu, Kai-Yuan Ting, Shang-Yun Hou, C. C. Lin, Wen-Chih Chiou, C.H. Tsai, Feng Wei Kuo, C. T. Wang, H. Hsia
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
One of the prominent challenges for widespread adoption of silicon photonics (SiPh) technology is the availability of an integration platform that can simultaneously meet a wide range of power, performance, and cost criteria in different applications
Autor:
H. Hsia, C. C. Lin, C. T. Wang, C.H. Tsai, Shang-Yun Hou, W. T. Chen, Kai-Yuan Ting, Douglas Yu
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
A logic-HBM2E power delivery system on a chip-on-wafer-on-substrate (CoWoS) platform with a deep trench capacitor (DTC) has been designed and analyzed for high performance computing (HPC) applications. The DTC integrated in the silicon interposer of
Autor:
Chung-Cheng Wu, T.H. Yu, Kai-Yuan Ting, Fang-Cheng Chen, C. T. Wang, C.H. Tsai, Douglas Yu, Shang-Yun Hou, Y.W. Lee, H. Hsia, W. C. Chiou
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
To accommodate the exceedingly demanding power integrity (PI) requirements for the advanced artificial intelligence (AI) and high performance computing (HPC) components, high-K (HK) based deep trench capacitors (DTC) have been integrated the first ti
Autor:
Victor C. Y. Chang, Kai-Yuan Ting, Shang-Yun Hou, Vincent Wei, T. H. Yu, Doug C. H. Yu, C. T. Wang, Chun-Yu Wu, S. Y. Huang, W. Chris Chen, Clark Hu
Publikováno v:
2017 Symposium on VLSI Technology.
State-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS®) has been applied for the first time in fabricating high performance wafer level system-in-package (WLSiP) containing the 2nd-generation high bandwidth memory (HBM2
Autor:
Shau-Lin Shue, H.H. Lu, H. Y. Huang, H. C. Chen, T. H. Liu, B. L. Lin, Cheng-Hsiung Tsai, Shang-Yun Hou, Y. H. Wu, C. W Shih, M. H. Hsieh, K. F. Cheng, H. H. Lee, C. W. Lu, Lee Ming-Han, C. L. Teng, C.H. Yu, Tien-I Bao, Chung-Ju Lee
Publikováno v:
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM).
High stresses generated from chip-package interactions (CPI), especially when large die is flip mounted on organic substrate using Pb-free C4 bumps, can easily cause low-k delamination. A novel scheme by applying an elastic material can effectively r
Autor:
H.C. Chu, Chia-Shiung Tsai, S.W. Huang, Hsien-Hsin Lin, W. S. Liao, Chung-Hao Tsai, S.P. Jeng, Doug C. H. Yu, C.Y. Pai, C.H. Chang, H.P. Hu, W.C. Chiang, Shang-Yun Hou, T.H. Liu
Publikováno v:
2014 IEEE International Electron Devices Meeting.
A reliability proven high-K (HK) metal-insulator-metal (MiM) structure has been verified within the silicon interposer in a chip-on-wafer-on-substrate (CoWoS) packaging for heterogeneous system-level decoupling application. The HK dielectric has an e
Autor:
H.Y. Lo, W. S. Liao, T.J. Wu, C. H. Fan, S.P. Jeng, Chen Tzu-Chiang, Cheng-Hsiang Hsieh, Doug C. H. Yu, W.M. Wu, C.C. Chiu, Chung-Shi Chiang, S.L. Chiu, Hsu-Hsien Chen, Shang-Yun Hou, L.C. Huang, W. C. Chiou
Publikováno v:
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.
A low-cost and manufacturable 3D IC substrate-less Chip-on-Wafer (CoW) package has been studied. The new structure is a result of process simplification from the production-proven Chip on Wafer on Substrate (CoWoS™) technology. It features three la
Autor:
Bahareh Banijamali, Suresh Ramalingam, Cheng-chieh Hsieh, Tsung-Shu Lin, Shin-Puu Jeng, Doug C. H. Yu, Chien-Chia Chiu, Clark Hu, Shang-Yun Hou, Liam Madden
Publikováno v:
2013 IEEE 63rd Electronic Components and Technology Conference.
TSV (Through Silicon Via)-based interposer has been proposed as a multi-die package solution to meet the rapidly increasing demand in inter-component (e.g. CPU, GPU and DRAM) communication bandwidth in an electronic system. The stacked-silicon die pa