Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Shang, Enming"'
Publikováno v:
Journal of Microelectronic Manufacturing, Vol 3, Iss 1, Pp 1-6 (2020)
With the continuous scaling in conventional CMOS technologies, the planar MOSFET device is limited by the severe short-channel-effect (SCE), Multi-gate FETs (MuG-FET) such as FinFETs and Nanowire, Nanosheet devices have emerged as the most promising
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e619363cd23b159fe11ca142212fa45b
http://www.jommpublish.org/p/50/
http://www.jommpublish.org/p/50/
Publikováno v:
Microwave and Optical Technology Letters. 63:2097-2102
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4e59a4fc3146c3e464ce1032fe2d4d5b
https://doi.org/10.1002/mop.32217
https://doi.org/10.1002/mop.32217
Publikováno v:
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT).
In this work, an improved TCAD based Design Technology Co-Optimization (DTCO) is proposed for gate-all-around (GAA) Nanosheet FET (NSFET) at 3 nm technology node. Based on conventional DTCO, only an additional procedure is introduced to extract the S
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3bf3d52141132962c5d27afca0f3acdf
https://doi.org/10.1109/icsict49897.2020.9278197
https://doi.org/10.1109/icsict49897.2020.9278197
Publikováno v:
2020 China Semiconductor Technology International Conference (CSTIC).
In this paper, we proposed a 5 nm FINFET device, which is based on typical 5 nm logic design rules. We have performed an optimization on the process parameters and iterate through device simulation with the consideration of current process capability
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1941568e93918baa5e2e3b0c6d9db4a3
https://doi.org/10.1109/cstic49141.2020.9282491
https://doi.org/10.1109/cstic49141.2020.9282491
Publikováno v:
2020 China Semiconductor Technology International Conference (CSTIC).
Since the logic 5 nm node still uses FinFET device, it still has room for device performance improvement since its first debut in the production of 16 nm node. The goal of this paper is to investigate the FinFET device optimization and Power Performa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::592054742309bc568f9313fa02af347d
https://doi.org/10.1109/cstic49141.2020.9282502
https://doi.org/10.1109/cstic49141.2020.9282502
Publikováno v:
2020 China Semiconductor Technology International Conference (CSTIC).
In the 5 nm FinFET design, more induced stress can bring charge mobility improvement and device performance. There are several influence factors on stress and mobility in the process design. Substrate orientation and channel direction combination is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::73f5dfdb5389ecbf54bc94b30dbd114f
https://doi.org/10.1109/cstic49141.2020.9282475
https://doi.org/10.1109/cstic49141.2020.9282475
Publikováno v:
Journal of Microelectronic Manufacturing, Vol 2, Iss 4 (2019)
In 5 nm technology node, FinFET device performance is sensitive to the dimension of the device structure such as the fin profile. In this work, we simulate the influence of fin height and fin width to an n-type FinFET. We have found that an optimized
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::da82f36e19cdeacef18561c0509ec11e
http://www.jommpublish.org/p/44/#
http://www.jommpublish.org/p/44/#
Publikováno v:
Microwave & Optical Technology Letters; Aug2021, Vol. 63 Issue 8, p2097-2102, 6p
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