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of 9
pro vyhledávání: '"Shailender Chaudhry"'
Autor:
Shailender Chaudhry, Martin Karlsson, Sherman H. Yip, Magnus Ekman, Robert E. Cypher, Håkan E. Zeffer, Anders Landin, Marc Tremblay
Publikováno v:
IEEE Micro. 29:6-16
Rock, Sun's third-generation chip-multithreading processor, contains 16 high-performance cores, each of which can support two software threads. Rock uses a novel checkpoint-based architecture to support automatic hardware scouting under a load miss,
Autor:
I. Parulkar, Peter F. Lai, Georgios Konstadinidis, Yuefei Ge, S. Parampalli, Marc Tremblay, Ilyas Elkin, Mamun Rashid, Y. Otaguro, Shailender Chaudhry, Leonard D. Rarick, Rambabu Pyapali, Y. Orginos, S. Gundala, M. Steigerwald
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:7-17
This third-generation Chip-Multithreading (CMT) SPARC processor consists of 16 cores with shared memory architecture and supports a total of 32 main threads plus 32 scout threads. It is targeted for high-performance servers, and is optimized for both
Publikováno v:
IEEE Micro. 25:32-45
CMT processors offer a way to significantly improve the performance of computer systems. The return on investment for multithreading is among the highest in computer microarchitectural techniques. If you design a core from scratch to support multithr
Publikováno v:
IEEE Micro. 20:12-25
The MAJC architecture enhances application performance by exploiting parallelism at multiple levels-instruction, data, thread, and process. Supporting vertical multithreading, speculative multithreading, and chip multiprocessors, the scalable VLIW ar
Autor:
Robert E. Cypher, Magnus Ekman, Shailender Chaudhry, Sherman H. Yip, Håkan E. Zeffer, Martin Karlsson, Marc Tremblay, Anders Landin
Publikováno v:
ISCA
This paper presents Simultaneous Speculative Threading (SST), which is a technique for creating high-performance area- and power-efficient cores for chip multiprocessors. SST hardware dynamically extracts two threads of execution from a single sequen
Autor:
Shailender Chaudhry
Publikováno v:
2008 IEEE Hot Chips 20 Symposium (HCS).
Autor:
Marc Tremblay, Shailender Chaudhry
Publikováno v:
Java Microarchitectures ISBN: 9781461353416
In this chapter, we describe a technique called Space-Time Dimensional Computing (STC) for exploiting parallelism in Java programs at method and loop level. We also describe the mechanisms in the MAJC (pronounced like magic) architecture and its firs
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::44dc9c8fd071195f76e2c767dfef5aee
https://doi.org/10.1007/978-1-4615-0993-6_9
https://doi.org/10.1007/978-1-4615-0993-6_9
Autor:
Shailender Chaudhry, Alok Choudhary
Publikováno v:
SPIE Proceedings.
Multimedia data is isochronous in nature and entails managing and delivering high volumes of data. Multiprocessors with their large processing power, vast memory, and fast interconnects, are an ideal candidate for the implementation of multimedia app
Conference
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