Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Shady Agwa"'
Autor:
Shady Agwa, Themis Prodromakis
Publikováno v:
Frontiers in Nanotechnology, Vol 5 (2023)
The applications of the Artificial Intelligence are currently dominating the technology landscape. Meanwhile, the conventional Von Neumann architectures are struggling with the data-movement bottleneck to meet the ever-increasing performance demands
Externí odkaz:
https://doaj.org/article/9912dfa7dd734871a46011e8bc083200
Autor:
Ting-Jung Chang, Ang Li, Fei Gao, Tuan Ta, Georgios Tziantzioulis, Yanghui Ou, Moyang Wang, Jinzheng Tu, Kaifeng Xu, Paul J. Jackson, August Ning, Grigory Chirkov, Marcelo Orenes-Vera, Shady Agwa, Xiaoyu Yan, Eric Tang, Jonathan Balkind, Christopher Batten, David Wentzlaff
Publikováno v:
2023 IEEE Custom Integrated Circuits Conference (CICC).
Autor:
Khalid Al-Hawaj, Tuan Ta, Nick Cebry, Shady Agwa, Olalekan Afuye, Eric Hall, Courtney Golden, Alyssa B. Apsel, Christopher Batten
Publikováno v:
2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA).
Publikováno v:
2022 IEEE International Symposium on Circuits and Systems (ISCAS).
Autor:
Andrea Mifsud, Jiawei Shen, Peilong Feng, Lijie Xie, Chaohan Wang, Yihan Pan, Sachin Maheshwari, Shady Agwa, Spyros Stathopoulos, Shiwei Wang, Alexander Serb, Christos Papavassiliou, Themis Prodromakis, Timothy G. Constandinou
Publikováno v:
2022 IEEE International Symposium on Circuits and Systems (ISCAS)
Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerg
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ad2d6ffcf682c5a099bbfd74f4d2ea56
Publikováno v:
ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC).
Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator using In-Situ Processing-In-SRAM
Publikováno v:
ISCAS
Vector accelerators can efficiently execute regular data-parallel workloads, but they require expensive multi-ported register files to feed large vector ALUs. Recent work on in-situ processing-in-SRAM shows promise in enabling area-efficient vector a
Publikováno v:
NOCS
Manycore processors are now integrating up to 1000 simple cores into a single die, yet these processors still rely on high-diameter mesh on-chip networks (OCNs) without complex flow-control nor custom circuits due to three reasons: (1) manycores requ
Autor:
Shady Agwa, Shunning Jiang, Cheng Tan, Yanghui Ou, Christopher Torng, Christopher Batten, Peitian Pan
Publikováno v:
ICCD
There is a growing interest in the open-source hardware movement to amortize non-recurring engineering costs by using plug-and-play system-on-chip (SoC) designs, where the communication among different components is provided by an on-chip interconnec
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 65:1909-1918
Nowadays, the high power density and the process, voltage, and temperature variations became the most critical issues that limit the performance of the digital integrated circuits because of the continuous scaling of the fabrication technology. Dynam