Zobrazeno 1 - 10
of 24
pro vyhledávání: '"Seyeon Yoo"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 58:78-89
Publikováno v:
IEEE Journal of Solid-State Circuits. 57:2829-2840
This work presents an ultra-low jitter, direct W-band phase-locked loop (PLL). Using the proposed power-gating injection-locked frequency multiplier (PG-ILFM)-based phase detector (PD) that can maintain a high phase-error-detection gain even at high
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:298-309
This work presents a low-jitter, low-reference-spur ring voltage-controlled oscillator (ring VCO)-based injection-locked clock multiplier (ILCM). Since the proposed triple-point frequency/phase/slope calibrator (TP-FPSC) can accurately remove the thr
Publikováno v:
2022 IEEE International Solid- State Circuits Conference (ISSCC).
Autor:
Younghyun Lim, Jooeun Bang, Taeho Seong, Yongsun Lee, Jaehyouk Choi, Jeonghyun Lee, Seyeon Yoo
Publikováno v:
IEEE Solid-State Circuits Letters. 2:305-308
A digital low-dropout (LDO) voltage regulator using a single-VCO-based edge-racing time quantizer (SVER TQ) was designed to achieve a fast-transient response and a high-accuracy of the output voltage. As the sampling frequency generated from the SVER
Publikováno v:
ESSCIRC
This work presents a fast-transient and low-power, external-clock-less digital low-dropout regulator (DLDO) using a wide-range adaptive sampling frequency, $f_\text{SP}$ . To generate such an $f_\text{SP}$ , the proposed gear-shifting comparator (GSC
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:2501-2512
This paper presents a ring-type, digitally controlled oscillator (DCO)-based integer- ${N}$ digital phase-locked loop (DPLL) that can achieve low jitter and low reference spur concurrently. In order to minimize the quantization error, while consuming
Autor:
Seojin Choi, Yongsun Lee, Jeonghyun Lee, Younghyun Lim, Jaehyouk Choi, Seyeon Yoo, Yongwoo Jo
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:927-936
An ultra-low-jitter, ring- LC -hybrid injection-locked clock multiplier (ILCM) is presented to achieve a high multiplication factor of 114. The proposed hybrid ILCM cascades a ring-type voltage-controlled oscillator (VCO)-based ILCM and an LC -type V
Autor:
Seojin Choi, Chanwoong Hwang, Jaehyouk Choi, Heein Yoon, Yoonseo Cho, Suneui Park, Seyeon Yoo
Publikováno v:
ISSCC
As the utilization of the mm-wave spectrum becomes active, designers’ interests are shifting to even higher frequencies in the W-band. Given their potential use as carrier frequencies for the next-generation mobiles (i.e., beyond 5G), these W-band
Autor:
Juyeop Kim, Taeho Seong, Yongwoo Jo, Seojin Choi, Hangi Park, Younghyun Lim, Seyeon Yoo, Yongsun Lee, Jaehyouk Choi
Publikováno v:
ISSCC
Subsampling PLLs (SSPLLs) are attractive architectures to generate ultra-low-jitter RF signals due to their intrinsically high phase-error-detection gain, K SH . However, this high-gain operation of a sample-and-hold circuit (SH) also has a downside