Zobrazeno 1 - 10
of 234
pro vyhledávání: '"Seyed Ghassem Miremadi"'
As technology process node scales down, on-chip SRAM caches lose their efficiency because of their low scalability, high leakage power, and increasing rate of soft errors. Among emerging memory technologies, $Spin$ - $Transfer\; Torque\; Magnetic\; R
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1bbfad7194023c2605ac80f3a36e2ee6
http://arxiv.org/abs/2201.04373
http://arxiv.org/abs/2201.04373
Publikováno v:
IEEE Transactions on Dependable and Secure Computing. 16:651-664
Tag array in on-chip caches is one of the most vulnerable components to radiation-induced soft errors. Protecting the tag array in some processors is limited to error detection using the parity check, since the overheads of error correcting codes are
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::720d32aa324ab75a23c0271a7cef4ab5
https://doi.org/10.1109/tdsc.2017.2706263
https://doi.org/10.1109/tdsc.2017.2706263
Publikováno v:
IEEE Transactions on Emerging Topics in Computing. 7:435-446
Erasure codes are applied in storage systems including both Hard Disk Drive (HDD) and Solid State Disk (SSD) to protect arrays of disks against failures. Applying these codes in SSD-based systems incurs additional number of Program/Erase (P/E) cycles
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5f4b0a3635dbafef6e5a67fb07914032
https://doi.org/10.1109/tetc.2017.2693424
https://doi.org/10.1109/tetc.2017.2693424
Publikováno v:
IEEE Transactions on Emerging Topics in Computing. 7:481-492
Spin-Transfer Torque Random Access Memories (STT-RAMs) are a promising alternative to SRAMs in on-chip caches. STT-RAMs face with a high error rate in write operations due to stochastic switching. To alleviate this problem, Error-Correcting Codes (EC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::382a3e7e5624603b12f87556b7309595
https://doi.org/10.1109/tetc.2017.2701880
https://doi.org/10.1109/tetc.2017.2701880
Autor:
Seyed Ghassem Miremadi, Nezam Rohbani
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 18:205-213
Aging has become a critical CMOS reliability issue in nanoscales. In general, the aging effect is exhibited as an increase in the delay of the combinational parts and robustness degradation of memory structures. To monitor the aging state of the comb
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::83587bd3dd7e6548c8f1064fdd689f7c
https://doi.org/10.1109/tdmr.2018.2817369
https://doi.org/10.1109/tdmr.2018.2817369
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:3138-3151
Bias temperature instability (BTI) is known as one serious reliability concern in nanoscale technologies. BTI gradually increases the absolute value of threshold voltage ( $V_{\mathrm{ th}}$ ) of MOS transistors. The main consequence of $V_{\mathrm{
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5520c4ffc82ca4629c9e46feff373d3d
https://doi.org/10.1109/tvlsi.2017.2734839
https://doi.org/10.1109/tvlsi.2017.2734839
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36:1725-1738
Network on chip (NoC) is a scalable interconnection architecture for ever increasing communication demand between processing cores. However, in nanoscale technology size, NoC lifetime is limited due to aging processes of negative bias temperature ins
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::933f950078f818f4262a23b7974d1519
https://doi.org/10.1109/tcad.2017.2648817
https://doi.org/10.1109/tcad.2017.2648817
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 17:481-489
SRAM-based scratchpad memories (SPMs) used in embedded systems impose high leakage power. Designing SPMs based on non-volatile memories (NVMs) were proposed as NVMs have negligible leakage power. The main problem of utilizing NVMs across the SPM is t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5c0a68fab0bc141b7e4257a24c4b3f3b
https://doi.org/10.1109/tdmr.2017.2710089
https://doi.org/10.1109/tdmr.2017.2710089
Publikováno v:
IEEE Transactions on Multi-Scale Computing Systems. 3:181-192
The failure probability in SSDs increases when the number of Program/Erase (P/E) cycles increases. Traditionally, a group of SSDs are protected with parity disks, called SSD-based RAID. It has been shown that the reliability of RAIDs depends on the d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::13cdb07cfe1d623320effdc85a7dd2ad
https://doi.org/10.1109/tmscs.2016.2598746
https://doi.org/10.1109/tmscs.2016.2598746
Publikováno v:
IEEE Transactions on Parallel and Distributed Systems. 28:1564-1577
Due to serious problems of SRAM-based caches in nano-scale technologies, researchers seek for new alternatives. Among the existing options, STT-RAM seems to be the most promising alternative. With high density and negligible leakage power, STT-RAMs o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a511c9dc5d8f6a511b51df808e601bdd
https://doi.org/10.1109/tpds.2016.2628742
https://doi.org/10.1109/tpds.2016.2628742