Zobrazeno 1 - 10
of 40
pro vyhledávání: '"Sewook Hwang"'
Autor:
Yoonjae Choi, Sewook Hwang, Yeonho Lee, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Chulwoo Kim
Publikováno v:
IEEE Access, Vol 9, Pp 118907-118918 (2021)
This paper presents an area- and energy- efficient digital sub-sampling clock and data recovery (CDR) with combined adaptive equalizer and self-error corrector (SEC). Using the digitized phase difference between the incoming data and the full-rate ou
Externí odkaz:
https://doaj.org/article/24c827106237478c960a339a209603d6
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29:1567-1574
This article presents an receiver (RX) only equalization (ROE) technique that eliminates feed-forward equalization (FFE) in transmitter (TX) and bandwidth improved output driver without increment of power consumption. With a help of the proposed desi
Autor:
Chulwoo Kim, Hyunsu Park, Yeonho Lee, Jonghyuck Choi, Yoonjae Choi, Sewook Hwang, Jincheol Sim
Publikováno v:
IEEE Access, Vol 9, Pp 118907-118918 (2021)
This paper presents an area- and energy- efficient digital sub-sampling clock and data recovery (CDR) with combined adaptive equalizer and self-error corrector (SEC). Using the digitized phase difference between the incoming data and the full-rate ou
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 66:192-196
A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip without shielding the device that increases the system cost and weight. In a ${\Delta } {\Sigma }$ modulator
Autor:
Chulwoo Kim, Sang-Geun Bae, Jaehun Jun, Junyoung Song, Yeonho Lee, Yoonjae Choi, Sewook Hwang
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:463-475
This paper presents a new pin/energy-efficient data and clock signaling scheme, named braid clock signaling (BCS). This signaling scheme efficiently embeds clock information into the data stream without data overhead, unnecessary pins, and channels f
Autor:
Jonathan M. Rothberg, Lutsky Joseph, Nevada J. Sanchez, Kook Youn-Jae, Fife Keith G, Chiu Leung Kin, Jungwook Yang, Chao Chen, Tyler S. Ralston, Bob Ryan, Graham Peyton, Liewei Bao, J. R. Petrus, Mcmahill Daniel Rea, Sewook Hwang, Kailiang Chen, Hamid Soleimani
Publikováno v:
ISSCC
Point-of-care ultrasound (POCUS) is transforming healthcare worldwide as a diagnostic tool with the potential to significantly reduce the delay between symptom onset and initiation of therapy. Conventional POCUS systems are based on piezoelectric tra
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 65:331-342
A 1-V 10-Gb/s/pin single-ended transceiver with a controllable active inductor-based output driver and adaptively calibrated cascaded-equalizer with infinite impulse response and finite impulse response filters for a post-LPDDR4 interface in a 65-nm
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 64:2691-2702
We present a 1.62–5.4-Gb/s receiver for DisplayPort version 1.2a and propose an adaptive equalizer (EQ) with a peak-level comparison technique for eye measurement. A single comparator and an up/down unmatched-current charge pump are used to realize
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 64:650-654
This brief describes the design and implementation of a 250-Mb/s to 6-Gb/s single-loop referenceless clock and data recovery circuit. The clock frequency multiplier and the referenceless frequency acquisition circuit are used to cover a wide-range da
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:344-353
A 10 Gbits/s/pin graphics DRAM interface is developed in 65-nm CMOS technology. Several design techniques are proposed for high-speed operation in a noisy environment. A fast precharging data sampler guarantees high-speed sampling without the need fo