Zobrazeno 1 - 10
of 45
pro vyhledávání: '"Severine Cheramy"'
Autor:
Lucile Arnaud, Chantal Karam, F. Servant, Severine Cheramy, S. Borel, Frank Fournel, Thierry Mourier, C. Dubarry, N. Bresson, Mathilde Gottardi, G. Mauguen, M. Assous
Publikováno v:
MRS Communications. 10:549-557
Recent applications require vertical chip stacking to increase the performance of many devices without the need of advanced node components. Image sensors and vision systems will embed more and more smart functions, for instance, image processing, ob
Autor:
Shintaro Toguchi, Michael L. Alles, Laurent Brunet, Perrine Batude, Ronald D. Schrimpf, Severine Cheramy, Mariia Gorchichko, Stephane Moreau, Robert A. Reed, Daniel M. Fleetwood, Francois Andrieu, En Xia Zhang
Publikováno v:
IEEE Electron Device Letters. 41:637-640
Effects of additional thermal budget associated with a three-dimensional (3D) fabrication sequence are evaluated for the total-ionizing dose radiation response of fully depleted silicon-on-insulator (FD-SOI) MOSFETs. Current-voltage and low-frequency
Autor:
Emilie Bourjot, Noura Nadi, Frank Fournel, Loic Sanchez, Severine Cheramy, Nicolas Raynaud, C. Castan, Alice Bond, Pascal Metzger, N. Bresson
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
Die-to-wafer direct hybrid bonding process is foreseen as a key enabler of heterogeneous 3D integration. Hybrid bonding technologies were first developed on W2W assembly reaching 3D interconnection pitch of $1\mu\mathrm{m}$ . Recently, CEA-Leti demon
Autor:
Emmanuel Ollier, P. Coudrain, Pascal Vivet, Denis Dutoit, Severine Cheramy, Jean Charbonnier, Fabien Clermidy
Publikováno v:
2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Apr 2021, Hsinchu, Taiwan. pp.1-2, ⟨10.1109/VLSI-TSA51926.2021.9440082⟩
2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Apr 2021, Hsinchu, Taiwan. pp.1-2, ⟨10.1109/VLSI-TSA51926.2021.9440082⟩
With the era of massive multi-core architecture targeting cloud computing for exascale high performance computing (HPC) and big data applications, large scale multi-core are made possible thanks to advanced 3D integration technologies. This paper pre
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c3e1a1adedcc6c551b1a32a45f917dbb
https://cea.hal.science/cea-03759922
https://cea.hal.science/cea-03759922
Autor:
Guillaume Moritz, Gael Pillonnet, Frédéric Berger, Denis Dutoit, Alexandre Arriordaz, David Coriat, Lucile Arnaud, Julian Pontes, Eric Guthmuller, Christian Bernard, Fabien Clermidy, Alexis Farcy, Didier Varreau, P. Coudrain, Alain Greiner, J. Durupt, Michel Harrand, Didier Lattard, Quentin L. Meunier, Jean Charbonnier, Ivan Miro-Panades, Sebastien Thuries, Cesar Fuguet, Arnaud Garnier, Severine Cheramy, Alain Gueugnot, Pascal Vivet, Yvain Thonnart
Publikováno v:
IEEE Journal of Solid-State Circuits
IEEE Journal of Solid-State Circuits, Institute of Electrical and Electronics Engineers, 2021, 56 (1), pp.79-97. ⟨10.1109/JSSC.2020.3036341⟩
IEEE Journal of Solid-State Circuits, 2021, 56 (1), pp.79-97. ⟨10.1109/JSSC.2020.3036341⟩
IEEE Journal of Solid-State Circuits, Institute of Electrical and Electronics Engineers, 2021, 56 (1), pp.79-97. ⟨10.1109/JSSC.2020.3036341⟩
IEEE Journal of Solid-State Circuits, 2021, 56 (1), pp.79-97. ⟨10.1109/JSSC.2020.3036341⟩
In the context of high-performance computing, the integration of more computing capabilities with generic cores or dedicated accelerators for artificial intelligence (AI) application is raising more and more challenges. Due to the increasing costs of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d4012e9cdfa24d7a486fffa94ba46e77
https://hal.archives-ouvertes.fr/hal-03072959/document
https://hal.archives-ouvertes.fr/hal-03072959/document
Autor:
Severine Cheramy, P.-Y. Martinez, A. Philippe, P. Coudrain, Yvain Thonnart, Arnaud Garnier, Fabien Clermidy, Eric Guthmuller, Pascal Vivet, Denis Dutoit, Didier Lattard, Jean Charbonnier
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM)
2020 IEEE International Electron Devices Meeting (IEDM), Dec 2020, San Francisco, United States. pp.15.3.1-15.3.4, ⟨10.1109/IEDM13553.2020.9372037⟩
2020 IEEE International Electron Devices Meeting (IEDM), Dec 2020, San Francisco, United States. pp.15.3.1-15.3.4, ⟨10.1109/IEDM13553.2020.9372037⟩
Supercomputers will soon achieve Exascale-level computing performances mainly thanks to the introduction of innovative hardware technologies around the processors. This article explains architectural and performance evolutions and describes how 3D in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6975e2d9dd986db359f87512f6a17c97
https://cea.hal.science/cea-03759943
https://cea.hal.science/cea-03759943
Autor:
Lucile Arnaud, David Coriat, Cesar Fuguet, Perceval Coudrain, Julian Pontes, Ivan Miro-Panades, Sebastien Thuries, J. Durupt, Didier Varreau, D. Lattard, Alexis Farcy, Alexandre Arriordaz, Eric Guthmuller, Alain Greiner, Christian Bernard, Severine Cheramy, Gael Pillonnet, Guillaume Moritz, Alain Gueugnot, Yvain Thonnart, Quentin L. Meunier, Frédéric Berger, Jean Charbonnier, Pascal Vivet, Fabien Clermidy, Michel Harrand, Arnaud Garnier, Denis Dutoit
Publikováno v:
ISSCC
In the context of high-performance computing and big-data applications, the quest for performance requires modular, scalable, energy-efficient, low-cost manycore systems. Partitioning the system into multiple chiplets 3D-stacked onto large-scale inte
Autor:
J. Durupt, Dominique Drouin, Yann Beilliard, P.-Y. Martinez, Severine Cheramy, David Danovitch, A. Philippe, Arnaud Garnier, P. Coudrain, C. Fuguet Tortolero, Pascal Vivet, Denis Dutoit, Didier Lattard, Jean Charbonnier, Maxime Godard, V. Mengue, Eric Guthmuller
Publikováno v:
2020 IEEE Symposium on VLSI Technology
2020 IEEE Symposium on VLSI Technology, Jun 2020, Honolulu, IEEE, pp.1-2, 2020, ⟨10.1109/VLSITechnology18217.2020.9265100⟩
2020 IEEE Symposium on VLSI Technology, Jun 2020, Honolulu, IEEE, pp.1-2, 2020, ⟨10.1109/VLSITechnology18217.2020.9265100⟩
In the context of high performance computing (HPC), energy efficiency and computing density are key for targeting exascale architectures. Close integration of chiplets, active interposer and field programmable gate arrays (FPGA) paves the way for den
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a8eb74a04d96315b4fab0e767614ffcd
https://hal.archives-ouvertes.fr/hal-03178715
https://hal.archives-ouvertes.fr/hal-03178715
Autor:
D. Scevola, Severine Cheramy, G. Mauguen, Loic Sanchez, E. Lagoutte, G. Romano, M. Zussy, N. Bresson, Jerome Dechamp, A. Jouve, E. Bourjot, Emmanuel Rolland, C. Dubarry, C. Castan, V. Balan, P. Stewart, Frank Fournel
Publikováno v:
3DIC
Die-to-wafer stacking is very promising for the next 3DIC generation since it offers the ability to assemble several dies with small interconnection pitches. This paper proposes an overall integration scheme D2W HB process to reinforce its robustness
Autor:
Christophe Brun, Xavier Baillin, Aurelie Thuaire, Delphine Sordes, Corentin Carmignani, Emmanuel Rolland, Patrick Reynaud, Severine Cheramy, Gilles Poupon
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 6:1804-1814
With their attractive intrinsic properties, such as morphology, autoassembling properties, and tailorability, nano-objects could provide alternative and innovative routes to current microelectronics and nanoelectronics. Further insight on their elect