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Autor:
Jongwook Park, Jung-Hwan Choi, Seung-Jun Bae, Si-Hyeong Cho, Seunseob Lee, Young-Ryeol Choi, In-Dal Song, Kwang-Il Park, Ki-Ho Kim, Jin-Seok Heo, Young-Soo Sohn, Dong-Hun Lee, Eunsung Seo, Junha Lee, Gil-Hoon Cha, Hyuck-Joon Kwon, Jin-Hyeok Baek, Daesik Moon, Youn-sik Park, Kyung-Soo Ha, Chang-Kyo Lee, Seok-Hun Hyun, Seong-Jin Jang
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:2906-2916
This paper presents a dual-loop two-step ZQ calibration scheme with a 20-nm DRAM process to support dedicated supply voltages ( $V_{DD}$ and $V_{DDQ}$ ). The proposed calibration scheme improves system signal integrity by maintaining the targeted out