Zobrazeno 1 - 10
of 109
pro vyhledávání: '"Seung-Chul Song"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:2304-2315
A self-timed pulsed latch (STPL) is proposed for low $V_{\mathrm {DD}}$ operation. By comparing input and output, the transparency window is adaptively generated in STPL, which resolves the hold time problem of the conventional pulsed latch. The meas
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26:609-620
A novel high-speed and highly reliable sense-amplifier-based flip-flop with transition completion detection (SAFF-TCD) is proposed for low supply voltage ( $V_{\mathrm {DD}}$ ) operation. The SAFF-TCD adopts the internally generated detection signal
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 63:1023-1032
Although near-threshold voltage (NTV) operation is an attractive means of achieving high energy efficiency, it can degrade the circuit stability of static random access memory (SRAM) cells. This paper proposes an NTV 7T SRAM cell in a 14 nm FinFET te
Publikováno v:
Journal of the Korean society for railway. 19:213-223
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23:2748-2752
Although near-threshold ( $V_{\mathrm {\mathbf {th}}}$ ) operation is an attractive method for energy and performance-constrained applications, it suffers from problems in terms of circuit stability, particularly, for static random access memory (SRA
Autor:
Ukjin Jung, Young Gon Lee, James Walter Blatchford, Brian K. Kirkpatrick, Hiroaki Niimi, Younggy Kim, Seung-Chul Song, Jin Ju Kim, Byoung Hun Lee
Publikováno v:
Microelectronic Engineering. 142:1-6
Gate leakage current is reduced up to 24% using a highly doped polysilicon gate/nitrided oxide gate stack. Interestingly, various factors that could affect the gate leakage current such as equivalent oxide thickness (EOT), overlap capacitance, gate d
Publikováno v:
IEEE Transactions on Electron Devices. 62:1754-1759
A figure of merit (FOM) for a CMOS system on chip (SoC) is proposed to correctly assess different CMOS SoCs in the near-threshold voltage ( $V_{{\rm {th}}})$ region, where the supply voltage ( $V_{{\rm {DD}}})$ is slightly higher than $V_{{\rm {th}}}
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 62:1538-1545
As the semiconductor technology scales down, the read stability and write ability of a static random-access memory (SRAM) cell are degraded because of the increased mismatch among its transistors. Extremely thin silicon-on-insulator is one of the att
Autor:
Hanwool Jeong, Juhyun Park, Seong-Ook Jung, Joseph Wang, Younghwi Yang, Seung Chul Song, Geoffrey Yeap
Publikováno v:
IEEE Transactions on Electron Devices. 62:1698-1704
A near-threshold voltage ( $V_{{\rm {th}}}$ ) operation circuit is important for both energy- and performance-constrained applications. The conventional 6-T SRAM bit-cell designed for super- $V_{{\rm {th}}}$ operation cannot achieve the target SRAM b
Autor:
Jason C. S. Woo, Joseph Wang, P. R. Chidi Chidambaram, Seung Chul Song, Frank Yang, Po-Yen Chien, Geoffrey Yeap
Publikováno v:
Microelectronics Reliability. 54:1090-1095
Continued scaling of transistor has resulted in severe short channel effects and transport degradation. In addition, variability in deeply scaled transistor such as threshold voltage ( V TH ) variability has emerged as a major challenge for circuit a