Zobrazeno 1 - 10
of 133
pro vyhledávání: '"Seung Tak Ryu"'
Autor:
Lizhen Zhang, Bo Gao, Kun-Woo Park, Kent Edrian Lozada, Raymond Mabilangan, Hyeongjin Kim, Jianhui Wu, Seung-Tak Ryu
Publikováno v:
IEEE Open Journal of Circuits and Systems, Vol 5, Pp 349-364 (2024)
In this paper, we propose a correlation-based background linearity calibration technique to digitally correct the bit weights in successive approximation register (SAR)-assisted analog-to-digital converters (ADCs). Unlike typical dithering-based cali
Externí odkaz:
https://doaj.org/article/85e74ffc8e6f4519873f5954b8bf762e
Publikováno v:
IEEE Open Journal of the Solid-State Circuits Society, Vol 4, Pp 163-175 (2024)
The distinct advantages of low power consumption and hardware compactness make SAR ADCs especially appealing in scaled CMOS technologies, garnering significant attention. The residue left on the capacitor digital-to-analog converter (CDAC) after conv
Externí odkaz:
https://doaj.org/article/260cf35c7d72496bae624ae6ed868b05
Publikováno v:
IEEE Access, Vol 9, Pp 117554-117564 (2021)
This paper proposes design strategies for a low-cost quantized neural network. To prevent the classification accuracy from being degraded by quantization, a structure-design strategy that utilizes a large number of channels rather than deep layers is
Externí odkaz:
https://doaj.org/article/f24af48fe02b428b9247bf369bc643c1
Autor:
John Hong, Sean Andrews, Jan Bos, Edward Chan, Tallis Chang, Vincent Condito, Alan Lewis, Murilo Pessatti, Seung Tak Ryu, Heesun Shin, Bing Wen
Publikováno v:
IEEE Transactions on Terahertz Science and Technology. 13:200-208
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2002ceea5ae0bc989fec6556012da9fe
https://doi.org/10.1109/tthz.2023.3263629
https://doi.org/10.1109/tthz.2023.3263629
Autor:
Kent Edrian Lozada, Il-Hoon Jang, Gyeom-Je Bae, Dong-Hun Lee, Ye-Dam Kim, Hankyu Lee, Seong Joong Kim, Seung-Tak Ryu
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 69:3635-3639
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::83abe379b16193abb32e827520f8b557
https://doi.org/10.1109/tcsii.2022.3182406
https://doi.org/10.1109/tcsii.2022.3182406
Publikováno v:
IEEE Journal of Solid-State Circuits. 57:2791-2801
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::db031b92b27d729b413c6f8f7832b95d
https://doi.org/10.1109/jssc.2022.3159569
https://doi.org/10.1109/jssc.2022.3159569
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:2691-2700
This article presents a relative-prime-based time-interleaved (RP TI) sub-ranging successive-approximation register (SAR) analog-to-digital converter (ADC) with on-chip background skew calibration. The proposed calibration aligns the sampling time of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5ced3becb66ce169924750b7bbf6355c
https://doi.org/10.1109/jssc.2021.3073976
https://doi.org/10.1109/jssc.2021.3073976
Autor:
Dong-Jin Chang, Seung-Tak Ryu
Publikováno v:
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e46b87d98fb79a1d989aed74cb71d0d7
https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830416
https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830416
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:1216-1226
An 8-bit 1-GS/s asynchronous loop-unrolled (LU) successive approximation register (SAR)-Flash hybrid analog-to-digital converter (ADC) with complementary dynamic amplifiers (CDAs) is presented. The proposed ADC is a combination of an asynchronous LU-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::85f49fd39d82725baf1f9f108f07e746
https://doi.org/10.1109/jssc.2020.3044624
https://doi.org/10.1109/jssc.2020.3044624
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 67:5189-5199
This paper demonstrates a compact mixed-signal (MS) convolutional neural network (CNN) design procedure by proposing a MS modular neuron unit that alleviates analog circuit related design issues such as noise. Through the first step of the proposed p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9022d68f7437483215ecea9acbb3e463
https://doi.org/10.1109/tcsi.2020.3007447
https://doi.org/10.1109/tcsi.2020.3007447