Zobrazeno 1 - 10
of 54
pro vyhledávání: '"Seung Moon Yoo"'
Autor:
Jai-Hoon Sim, Kyu-Chan Lee, Nam-jong Kim, Soo-In Cho, Hongil Yoon, Byung-sik Moon, Dong-ryul Ryu, Seung-Moon Yoo, Changhyun Kim, Sang-Bo Lee, Keum-Yong Kim, Jei-Hwan Yoo
Publikováno v:
IEEE Journal of Solid-State Circuits. 32:642-648
This paper describes several new circuit design techniques for low V/sub CC/ regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (/spl Delta/V/sub BL/) as well as the V/sub GS/ margin by boosti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c07d12644c9745a83e883124a2740643
https://doi.org/10.1109/4.568824
https://doi.org/10.1109/4.568824
Autor:
Keum-Yong Kim, Ejaz Haq, Kye-Hyun Kyung, Kinam Kim, Bok-Moon Kang, Moon-Hae Son, Chang-Hyun Kim, Hyung-Kyu Lim, Soo-In Cho, K. H. Lee, Jai-Hoon Sim, Sang-Bo Lee, Jae-Gwan Park, Jong-Woo Park, Jung-Hwa Lee, Seung-Moon Yoo, Jei-Hwan Yoo, Joungho Kim, Jinman Han, Byung-sik Moon, Kang-yoon Lee, Kyu-Chan Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:1635-1644
This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V/sub cc/=2.0 V and 25/spl deg/C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fe8f35bf377499dd5f1a434eea274fb8
https://doi.org/10.1109/jssc.1996.542308
https://doi.org/10.1109/jssc.1996.542308
Autor:
Wei Huang, Josep Torrellas, Vinh Lam, Pratap Pattnaik, Yi Kang, Zhenzhou Ge, Diana Keen, Seung-Moon Yoo
Publikováno v:
ICCD
Major advances in merged logic DRAM (MLD) technology coupled with the popularization of memory-intensive applications provide fertile ground for architectures based on intelligent memory (IRAM) or processors-in-memory (PIM). The contribution of this
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3b24a085b47d6154b09cda8ac1a74cb8
https://doi.org/10.1109/iccd.2012.6378608
https://doi.org/10.1109/iccd.2012.6378608
Publikováno v:
IEEE Journal of Solid-State Circuits. 28:499-503
Wide-voltage-range DRAMs with extended data retention are desirable for battery-operated or portable computers and consumer devices. The techniques required to obtain wide operation, functionality, and performance of standard DRAMs from 1.8 V (two Ni
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::abc33c997fe8ea4095ce53ac452bf0b3
https://doi.org/10.1109/4.210034
https://doi.org/10.1109/4.210034
Autor:
Chan Jong Park, Jung-Hwa Lee, Sei Seung Yoon, Hyung-Dong Kim, Dong Il Seo, Ejaz Haq, Byung-Chul Kim, Seung-Moon Yoo, Jeong Se-Jin, Chang Gyu Hwang, Tae-Seong Jang, Jin Man Han, Chang Sik Choi, Soo-In Cho
Publikováno v:
Proceedings of 1994 IEEE Symposium on VLSI Circuits.
A 256M DRAM featuring register controlled low power self refresh without toggling of internal addresses or predecoders, activation of all row lines in quick succession for rapid burn-in at wafer level and hierarchical I/O line scheme with flexible re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ba86bc2d54e13242f05a53bff80c064b
https://doi.org/10.1109/vlsic.1994.586228
https://doi.org/10.1109/vlsic.1994.586228
Publikováno v:
DAC
High-speed communications link cores must consume low-power, feature, low bit-error-rates (BER), and address many applications. We pFsent a methodology to design adaptive link architectures, whereby the link's intemal logic complexity, frequency, and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4a8d234cf5d3010c73d989fbe0145a13
https://doi.org/10.1145/996566.996598
https://doi.org/10.1145/996566.996598
Publikováno v:
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..
Supply-voltage reduction is a known technique for reducing CMOS active power. We propose a semi-custom voltage-island approach based on internal regulation and selective custom design. This approach enables transparent embedding, since no additional
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0040d324c79a8473adb92c5a66bce5ff
https://doi.org/10.1109/lpe.2003.1231836
https://doi.org/10.1109/lpe.2003.1231836
Publikováno v:
Great Lakes Symposium on VLSI
In this paper, we describe NMOS Energy Recovery Logic (NERL) which exhibits high throughput with low energy consumption due to efficient energy transfer and recovery using adiabatic and bootstrapping techniques. NERL shows full output voltage swing,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6e9a6c975d96abdd5a0b3e3f7ae8dd76
https://doi.org/10.1109/glsv.1999.757440
https://doi.org/10.1109/glsv.1999.757440
Autor:
Sung-Mo Kang, Seung-Moon Yoo
Publikováno v:
Great Lakes Symposium on VLSI
This paper describes no-race charge-recycling differential logic (NCDL) which realizes low power computation with less sensitivity to input signal skews. Performance comparison with previous charge recycling logics is shown for a 2-input NAND logic.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::14de5310621c78a774ab7126966f8eac
https://doi.org/10.1109/glsv.1999.757410
https://doi.org/10.1109/glsv.1999.757410
Autor:
Seung-Moon Yoo, Sung-Mo Kang
Publikováno v:
ISCAS (1)
This paper describes CMOS Pass-gate No-race Charge-recycling Logic (CPNCL). CPNCL realizes low power computation by using a charge sharing method without pre-evaluation problems. CPNCL operates in push-pull mode using CMOS pass-gate logic. 2-input NA
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ecb3aea683982ee5efe5b0e6c93cded7
https://doi.org/10.1109/iscas.1999.777844
https://doi.org/10.1109/iscas.1999.777844