Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Seung Han Ahn"'
Autor:
Woodward Yang, Jin-Yong Chung, Sea-Chung Kim, Eui-Kyu Ryou, Seung-Han Ahn, Jae-Kyung Wee, Joe-Sun Choi
Publikováno v:
IEEE Journal of Solid-State Circuits. 35:1408-1414
An antifuse EPROM and 3-V programming circuit has been demonstrated in an existing 0.22-/spl mu/m DRAM process technology and is fully compatible with 64-Mb SDRAM specifications. The antifuse circuitry uses an internal high-voltage generator for prog
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2f959a40b6c1054a29af8a60852b7845
https://doi.org/10.1109/4.871316
https://doi.org/10.1109/4.871316
Autor:
Jong-Hoon Oh, Young-Hee Kim, Kun-Woo Park, Jae-Ik Doh, Jae-Yoon Sim, Choon-Sik Oh, Seung-Han Ahn, Hong-June Park, Hyun-Woong Chung
Publikováno v:
IEEE Journal of Solid-State Circuits. 32:79-85
The occasional power-on latch-up phenomenon of DRAM modules with a data bus shared by multiple DRAM chips on different modules was investigated and the circuit techniques for latch-up prevention were presented. Through HSPICE simulations and measurem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::21a0d4af5cec950c7640f846ddd3440e
https://doi.org/10.1109/4.553181
https://doi.org/10.1109/4.553181
Publikováno v:
IEEE Journal of Solid-State Circuits. 32:92-99
A new register-based wave-pipelined scheme for synchronous DRAMs (SDRAMs) is proposed. In this scheme, (N-1) registers are located between a read data bus line pair and a data output buffer and (N-1) read data are stored in parallel in these register
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::119c92444a2421c3e3e964f137fc1ac0
https://doi.org/10.1109/4.553186
https://doi.org/10.1109/4.553186
Publikováno v:
ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).
This paper describes the architecture of a scalable shared buffer ATM switch and VLSI implementation. It provides scalability in port size and buffer size. The prototype chip has been designed for 4/spl times/4 ATM switch which has a shared buffer fo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d66e9312d3c9558306695ca2b30ac86d
https://doi.org/10.1109/iscas.1998.706853
https://doi.org/10.1109/iscas.1998.706853
Publikováno v:
VLSI Design
This paper proposes a new scalable memory architecture with pipeline technique and systolic data flow. We divided entire memory into N/spl times/N sub-memory blocks and placed them onto scalable two-dimensional array that has communication channel of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c50161694dcaad9928ac0d91940a9b43
https://doi.org/10.1109/icvd.1997.568086
https://doi.org/10.1109/icvd.1997.568086
Publikováno v:
Proceedings Tenth International Conference on VLSI Design; 1997, p257-260, 4p
Autor:
Jae-Kyung Wee, Woodward Yang, Eui-Kyu Ryou, Joe-Sun Choi, Seung-Han Ahn, Jin-Yong Chung, Sea-Chung Kim
Publikováno v:
IEEE Journal of Solid-State Circuits; Oct2000, Vol. 35 Issue 10, p1408-1414, 7p
Publikováno v:
IEEE Journal of Solid-State Circuits; 1997, Vol. 32 Issue 1, p92-99, 8p
Autor:
Young-Hee Kim, Jae-Yoon Sim, Hong June Park, Jae-Ik Doh, Kun-Woo Park, Hyun-Woong Chung, Jong-Hoon Oh, Choon-Sik Oh, Seung-Han Ahn
Publikováno v:
IEEE Journal of Solid-State Circuits; 1997, Vol. 32 Issue 1, p79-85, 7p
Publikováno v:
ISCAS '98 Proceedings of the 1998 IEEE International Symposium on Circuits & Systems (Cat No98CH36187); 1998, Issue 2, p109-109, 1p