Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Seth H. Pugsley"'
Publikováno v:
ISCA
Hardware prefetching is an effective technique for hiding cache miss latencies in modern processor designs. Prefetcher performance can be characterized by two main metrics that are generally at odds with one another: coverage, the fraction of baselin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::721735bd01c1b1f0e03b776f78a83b26
https://doi.org/10.1145/3307650.3322207
https://doi.org/10.1145/3307650.3322207
Autor:
Feifei Li, Al Davis, Vijayalakshmi Srinivasan, Seth H. Pugsley, Rajeev Balasubramonian, Alper Buyuktosunoglu, Jeffrey Jestes
Publikováno v:
IEEE Micro. 34:44-52
The emergence of 3D stacking and the imminent release of Micron's Hybrid Memory Cube (HMC) device have made it more practical to move computation near memory. This work presents a detailed analysis of in-memory MapReduce in the context of near-data c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::32abe57c05aec9e8d9ff63f375171caa
https://doi.org/10.1109/mm.2014.54
https://doi.org/10.1109/mm.2014.54
Autor:
Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A.L. Narasimha Reddy, Chris Wilkerson, Zeshan Chishti
Publikováno v:
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::51eeb21783ea5c09a20a5b1599cdee55
https://doi.org/10.1109/micro.2016.7783763
https://doi.org/10.1109/micro.2016.7783763
Autor:
Seth H. Pugsley, Sahil Koladiya, Manjunath Shevgoor, Zeshan A. Chishti, Christopher B. Wilkerson, Rajeev Balasubramonian
Publikováno v:
MICRO
Prior work in hardware prefetching has focused mostly on either predicting regular streams with uniform strides, or predicting irregular access patterns at the cost of large hardware structures. This paper introduces the Variable Length Delta Prefetc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c1fb9f3a7e2d0e9448ef88847bce057e
https://doi.org/10.1145/2830772.2830793
https://doi.org/10.1145/2830772.2830793
Publikováno v:
ICCD
A large fraction of MapReduce execution time is spent processing the Map phase, and a large fraction of Map phase execution time is spent sorting the intermediate key-value pairs generated by the Map function. Sorting accelerators can achieve high pe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fdcdb43cdb6105a3fec4a6c77b077a1e
https://doi.org/10.1109/iccd.2015.7357143
https://doi.org/10.1109/iccd.2015.7357143
Autor:
Gita Sreekumar, Ali Shafiee, Rajeev Balasubramonian, Hardik Jain, Mohit Tiwari, Akhila Gundu, Seth H. Pugsley
Publikováno v:
HASP@ISCA
Multiple virtual machines (VMs) are typically co-scheduled on cloud servers. Each VM experiences different latencies when accessing shared resources, based on contention from other VMs. This introduces timing channels between VMs that can be exploite
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b717b8c66e9f8a8c03eeeb9eb242c834
https://doi.org/10.1145/2611765.2611776
https://doi.org/10.1145/2611765.2611776
Autor:
Rajeev Balasubramonian, Huihui Zhang, Alper Buyuktosunoglu, Seth H. Pugsley, Jeffrey Jestes, Al Davis, Feifei Li, Vijayalakshmi Srinivasan
Publikováno v:
ISPASS
While Processing-in-Memory has been investigated for decades, it has not been embraced commercially. A number of emerging technologies have renewed interest in this topic. In particular, the emergence of 3D stacking and the imminent release of Micron
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b87d18a5d1aa0bf72c8639a96702ffdc
https://doi.org/10.1109/ispass.2014.6844483
https://doi.org/10.1109/ispass.2014.6844483
Autor:
Shih-Lien Lu, Peng-Fei Chuang, Aamer Jaleel, Kingsum Chow, Seth H. Pugsley, Christopher B. Wilkerson, Robert L. Scott, Zeshan A. Chishti, Rajeev Balasubramonian
Publikováno v:
HPCA
Memory latency is a major factor in limiting CPU performance, and prefetching is a well-known method for hiding memory latency. Overly aggressive prefetching can waste scarce resources such as memory bandwidth and cache capacity, limiting or even hur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::657f8077f74683a302baf0bf69436eee
https://doi.org/10.1109/hpca.2014.6835971
https://doi.org/10.1109/hpca.2014.6835971
Publikováno v:
PACT
Snooping and directory-based coherence protocols have become the de facto standard in chip multi-processors, but neither design is without drawbacks. Snooping protocols are not scalable, while directory protocols incur directory storage overhead, fre
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2fef8bf3318c67e6e8356a3afaded11e
https://doi.org/10.1145/1854273.1854331
https://doi.org/10.1145/1854273.1854331
Publikováno v:
PACT
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true for a large-scale distributed memory system where multiple transactions
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::228f1cfd46d364c41a3aa1f8e6fc451b
https://doi.org/10.1145/1454115.1454137
https://doi.org/10.1145/1454115.1454137