Zobrazeno 1 - 10
of 36
pro vyhledávání: '"Sergio Ruocco"'
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 65:3338-3348
This paper introduces the concept of time-based sensing (TBS) for bitcell read in spin transfer torque magnetic RAMs arrays. The TBS scheme converts the bitline voltage into time, then the sense amplifier discriminates the two bitcell levels in the t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0dcdae1981150693ed73bc3f94ec2251
https://doi.org/10.1109/tcsi.2018.2828611
https://doi.org/10.1109/tcsi.2018.2828611
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 65:1269-1278
This paper proposes a novel approach to enhance the STT-MRAMs read margin based on the concept of dynamic reference (DR). Our dynamic reference scheme dynamically adjusts the sense amplifier reference voltage according to the bitline voltage, aiming
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9998bc381d934b98b6192d59ce88cad2
https://doi.org/10.1109/tcsi.2017.2749522
https://doi.org/10.1109/tcsi.2017.2749522
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 63:1652-1660
This paper proposes a novel boosted voltage sensing (BVS) scheme that substantially improves the resiliency of STT-MRAMs against variations in read accesses based on bitline voltage sensing, and on a wide range of voltages. The BVS scheme mitigates t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6bb79533a62a486cb637576bd0ae08ac
https://doi.org/10.1109/tcsi.2016.2582203
https://doi.org/10.1109/tcsi.2016.2582203
Publikováno v:
ISCAS
This paper proposes a novel STT-MRAM sensing scheme based on time-based sensing (TBS). The TBS scheme converts the bitline voltage into time, then sensing is performed in the time domain rather than in conventional voltage or current domain. Monte Ca
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::29cb1b1ff2bfd9b9440a96c7c9b8d615
https://doi.org/10.1109/iscas.2018.8350966
https://doi.org/10.1109/iscas.2018.8350966
Publikováno v:
ISCAS
Web of Science
Web of Science
In this paper we show that the area optimization of STT-MRAM bitcells can deliver a substantial reduction in the energy per write access when dynamic voltage scaling (DVS) is adopted. Indeed, the increase in the bitcell area enables the reduction in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2350a0747a6c1092b1b9464356b1b0f3
https://doi.org/10.1109/iscas.2016.7539172
https://doi.org/10.1109/iscas.2016.7539172
Autor:
Duy-Khanh Le, Sergio Ruocco
Publikováno v:
ICCCRI
Performance and reliability are two core challenges for today's cloud data centers. Emerging non-volatile memory (NVM) technologies, which promise large capacity, high-speed, byte-addressable and persistent memory, can offer mitigating benefits. In p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d9b66e83b58b9b1461d47d22d6f01442
https://doi.org/10.1109/icccri.2015.29
https://doi.org/10.1109/icccri.2015.29
Publikováno v:
ISCAS
Web of Science
Web of Science
This paper investigates the impact of voltage scaling on the energy and the performance of STT-RAM bitcells during write operation. Analytical models of energy scaling and performance degradation are derived to gain an insight into the energy-perform
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7bdd52ec2276999f7feb49e69db412ec
https://doi.org/10.1109/iscas.2015.7169146
https://doi.org/10.1109/iscas.2015.7169146
Autor:
Sergio Ruocco
Publikováno v:
EURASIP Journal on Embedded Systems, Vol 2008, Iss 1, p 234710 (2008)
EURASIP Journal on Embedded Systems, Vol 2008 (2008)
EURASIP Journal on Embedded Systems, Vol 2008 (2008)
L4-embedded is a microkernel successfully deployed in mobile devices with soft real-time requirements. It now faces the challenges of tightly integrated systems, in which user interface, multimedia, OS, wireless protocols, and even software-defined r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::57a129c4506795ab3d5c398c09a729d7
http://jes.eurasipjournals.com/content/2008/234710
http://jes.eurasipjournals.com/content/2008/234710
Autor:
Sergio Ruocco
Publikováno v:
2006 27th IEEE International Real-Time Systems Symposium (RTSS'06); 2006, p246-256, 11p
Publikováno v:
Web of Science
ISCAS
ISCAS
Read access in STT-MRAMs is well known to be highly sensitive to process variations. Such variations are responsible for read bit error rates that are worse than conventional CMOS memories (e.g., SRAM) by orders of magnitude, especially at low voltag
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1ff8ad997a8e00028b4fb8d1bea2ed3f
https://publons.com/wos-op/publon/50479406/
https://publons.com/wos-op/publon/50479406/
