Zobrazeno 1 - 10
of 44
pro vyhledávání: '"Sergey V. Rylov"'
Autor:
Sergey V. Rylov
Publikováno v:
IEEE Transactions on Applied Superconductivity. 29:1-5
We have introduced a new class of dc-powered Single Flux Quantum (SFQ) logic that uses dynamic (self-resetting) internal states to achieve completely clock-free gate operation and provide high immunity to input data skew. We call it DSFQ (dynamic SFQ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::110ee20213a3bd4d807b542d1b22a72c
https://doi.org/10.1109/tasc.2019.2896137
https://doi.org/10.1109/tasc.2019.2896137
Autor:
Seongwon Kim, Jonathan E. Proesel, Sungjae Lee, Timothy O. Dickson, John F. Bulzacchelli, Mounir Meghelli, Zeynep Toprak-Deniz, Ilter Ozkaya, Herschel A. Ainspan, Alessandro Cevrero, Sergey V. Rylov, Daniel M. Kuchta
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:1214-1226
This paper presents a 32 Gb/s non-return-to-zero optical link using 850-nm vertical-cavity surface-emitting laser-based multi-mode optics with 14-nm bulk FinFET CMOS circuits. The target application is the integration of optics on to the first-level
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ca0034b6af481dc0c19b0988aac25148
https://doi.org/10.1109/jssc.2017.2778280
https://doi.org/10.1109/jssc.2017.2778280
Autor:
Benjamin G. Lee, Jonathan E. Proesel, Sergey V. Rylov, Christian W. Baks, Clint L. Schow, Abhijeet Ardey, Michael P. Beakes, Alexander V. Rylyakov, Ben Parker, Mounir Meghelli, John F. Bulzacchelli
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:3120-3132
We report a dc-coupled burst-mode (BM) receiver for optical links in a dynamically reconfigurable network. Through the introduction of interlocking search algorithms, a robust 25 Gb/s BM operation is achieved with 31 ns lock time. At the beginning of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::61c5fc311f875f26b09a12751bddaf2c
https://doi.org/10.1109/jssc.2015.2478837
https://doi.org/10.1109/jssc.2015.2478837
Autor:
Christian W. Baks, Sergey V. Rylov, Daniel J. Friedman, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Ping-Hsuan Hsieh, Jose A. Tierno, Ankur Agrawal, Young H. Kwark, Seongwon Kim, Lei Shan, Mark Ferriss, Alexander V. Rylyakov, Yong Liu, John F. Bulzacchelli, Benjamin D. Parker
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:1917-1931
A power-scalable 2 Byte I/O operating at 12 Gb/s per lane is reported. The source-synchronous I/O includes controllable TX driver amplitude, flexible RX equalization, and multiple deskew modes. This allows power reduction when operating over low-loss
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ad9cd40dac24c556b4a455339f5d887e
https://doi.org/10.1109/jssc.2015.2412688
https://doi.org/10.1109/jssc.2015.2412688
Autor:
Robert Callan, Thomas Morf, Herschel A. Ainspan, D. Furrer, Andrea Prati, Ping-Hsuan Hsieh, P. Buchmann, William R. Kelly, Daniel J. Friedman, David R. Hanson, Jon D. Garlett, Juergen Hertle, Daniel W. Storaska, J. A. Sorice, R. Kelkar, Matthias Brandli, Thomas Toifl, V. Sharma, Marcel Kossel, Daniele Gardellini, G. A. Ritter, John F. Bulzacchelli, Christian Menolfi, Troy J. Beukema, Sergey V. Rylov, L. R. Chieco
Publikováno v:
ISSCC
This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip communications over high-loss electrical channels such as backplanes. The equalization needed for such applications is provided by a 4-tap baud-spaced feed-forwar
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dcba9a7124e22fb3cac2a101caf74fe1
https://doi.org/10.1109/jssc.2012.2216414
https://doi.org/10.1109/jssc.2012.2216414
Autor:
Michael P. Beakes, Troy J. Beukema, Ankur Agrawal, Benjamin D. Parker, Peter Buchmann, Sergey V. Rylov, Mounir Meghelli, Yong Liu, Alexander V. Rylyakov, Zeynep Toprak-Deniz, Thomas Toifl
Publikováno v:
ISSCC
As CMOS devices continue to scale down in voltage and area, digital-based high-speed serial I/Os [1] become increasingly competitive with analog-based designs [2,3]. In addition to offering the PVT-independent performance of digital functions and sup
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0c37b4042f0599fe6414f4ccfac3243c
https://doi.org/10.1109/isscc.2016.7417904
https://doi.org/10.1109/isscc.2016.7417904
Autor:
Michael Wielgos, Sergey V. Rylov, Jieming Qi, Gautam Gangasani, Joseph Natonio, Jon D. Garlett, Todd M. Rasmus, Michael A. Sorna, William R. Kelly, Troy J. Beukema, John F. Bulzacchelli, Jong-Ru Guo, Michael J. Shannon, Mounir Meghelli, David A. Freitas, Chun-Ming Hsu, Hui H. Xu
Publikováno v:
CICC
This paper presents a 16-Gb/s 45-nm SOI CMOS transceiver for multi-standard backplane applications. The receiver uses a 12-tap DFE with circuit refinements for supporting higher data rates. Both the receiver and the transmitter use dynamic adaptation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::df2a414fb18fa33d69dd05fb23af18fe
https://doi.org/10.1109/jssc.2012.2196313
https://doi.org/10.1109/jssc.2012.2196313
Autor:
Yong Liu, John U. Knickerbocker, Xiaoxiong Gu, Paul S. Andry, Cornelia K. Tsang, Bing Dang, John F. Bulzacchelli, Daniel J. Friedman, Sergey V. Rylov, Herschel A. Ainspan, Benjamin D. Parker, Lavanya Turlapati, Timothy O. Dickson, Michael P. Beakes
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:884-896
A source synchronous I/O system based on high-density silicon carrier interconnects is introduced. Benefiting from the advantages of advanced silicon packaging technologies, the system uses 50 μm-pitch μC4s to reduce I/O cell size and fine-pitch in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::33f6f151920f35ece312be42edfebf81
https://doi.org/10.1109/jssc.2012.2185184
https://doi.org/10.1109/jssc.2012.2185184
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18:1043-1056
A high-throughput low-latency digital finite impulse response (FIR) filter has been designed for use in partial-response maximum-likelihood (PRML) read channels of modern disk drives. The filter is a hybrid synchronous-asynchronous design. The speed-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b5ced7a195e5180c8cc3a3a55d955e1a
https://doi.org/10.1109/tvlsi.2009.2019660
https://doi.org/10.1109/tvlsi.2009.2019660
Publikováno v:
IEEE Transactions on Applied Superconductivity. 19:1026-1033
In a superconductor digital-RF transmitter, the power amplifier chain can be implemented in hybrid temperature, hybrid technology environment, where the superconductor switching amplifier forms the first stage of the amplification chain. We have desi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9904a2a4515d272af2af50fdd0d64c4a
https://doi.org/10.1109/tasc.2009.2018413
https://doi.org/10.1109/tasc.2009.2018413