Zobrazeno 1 - 10
of 18
pro vyhledávání: '"Sergey Sofer"'
Autor:
Suhwan Kim, Harish K. Krlshnarnurthy, Sergey Sofer, Sheldon Weng, Shahar Wolf, Ashoke Ravi, Krishnan Ravichandran, Ofir Degani, James W. Tschanz, Vivek De
Publikováno v:
2023 IEEE International Solid- State Circuits Conference (ISSCC).
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 13:231-235
In this work, the impact of impedance mismatch between on-die CMOS drivers and driven transmission lines on electromigration (EM) and Joule-heating failure mechanisms has been qualitatively studied. Signals corrupted by the impedance mismatch were ex
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 12:363-368
In this paper, the impact of resonant voltage oscillations, triggered on on-die power supply and ground grids by switching of active elements, upon electromigration (EM) and Joule heating of the interconnects, constituting the grids, has been studied
Autor:
P. Livshits, Sergey Sofer
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 12:341-346
In this paper, the impact of crosstalk noise between two adjacent interconnection lines, namely, the aggressor and a victim line, upon electromigration (EM) and Joule-heating failure mechanisms in ULSI microchips has been studied. It was shown that t
Publikováno v:
Microelectronic Engineering. 92:119-122
The impact of increasing resistive losses of on-die metal interconnects upon device reliability and functionality has been studied. The signal waveforms experimentally measured at the far-end of on-die transmission lines (45nm CMOS technology test ch
Autor:
P. Livshits, Sergey Sofer
Publikováno v:
The Open Optics Journal. 5:66-73
In this paper, the ways to improve the functionality and reliability of Digital Signal Processors, used to support optical networks, have been studied. Specifically, supported on our finding from previous experimental studies that on-die global inter
Publikováno v:
2012 IEEE International Integrated Reliability Workshop Final Report.
In this work, novel configurations of rarely switching ULSI I/O circuits, which provide a "refresh" operation allowing for temporal bias removal without any changes in the logic state or electrical characteristics of these circuits, are presented. Th
Publikováno v:
MTV
Proposed a way to increase the coverage of power distribution network verification, especially applicable for designs, employing distributed power gating switches. It includes defining of amount of CMOS devices (in the same cluster) simultaneously to
Publikováno v:
2011 IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems (COMCAS 2011).
Described an importance, complexity and limitations of power distribution network analysis in Deep Submicron Designs. Proposed a three-stage way of Power Integrity (PI) checks to account for standard PI tools' capacity limitation of on-die short and
Publikováno v:
VLSI-SoC
A duty cycle correction (DCC) circuit with deterministic clock insertion delay is presented. To neutralize the ambiguity of the DCC circuit insertion delay induced by the wide range of input clock duty cycle, a signal differentiating circuit at the i