Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Sergey Shumarayev"'
Publikováno v:
2022 IEEE Hot Chips 34 Symposium (HCS).
Autor:
Michael D. Hutton, Hae-Chang Lee, Jeffrey Tyhach, Dong-myung Choi, Arifur Rahman, Edwin Yew Fatt Kok, Jack Chui, Martin Langhammer, Boon-Jin Ang, David Lewis, Ket Chiew Sia, Wei-Yee Koay, Tim Tri Hoang, Dan Oh, Brad Vest, Atsatt Sean R, Sergey Shumarayev, Allen Chan
Publikováno v:
CICC
This paper presents the architecture of Arria 10, a high-density FPGA family built on the TSMC 20SOC process. The design of the device includes an embedded dual-core 1.5 GHz ARM A9 subsystem with peripherals, more than 1M logic elements (LEs) and 1.7
Publikováno v:
ITC
Moving to the latest submicron node is required for digital scaling but causes many challenges for analog design. Additionally, scaling pushes the need for higher bandwidth. Data rates up to 28Gbps require effectively dealing with random variations a
Autor:
Sergey Shumarayev, Dan Mansur
Publikováno v:
2010 IEEE Hot Chips 22 Symposium (HCS).
This article consists of a collection of slides from the author's conference presentation on Altera's 28-nm Stratix V FPGA product line. Some of the specific topics discussed include: the special features, system specifications, and system design for
Autor:
Sergey Shumarayev, Mike Peng Li
Publikováno v:
CICC
We first review the signaling and jitter requirements for emerging high-speed wireline communication standards at ∼10 Gbps, including CEI 11G, XLAUI/CAUI, XFI, and SFP+. We then present an FPGA transceiver architecture and subsystem/circuit blocks
Autor:
Wilson Wong, Tim Tri Hoang, Tung Hoang Tran, Tam Nguyen, Sergey Shumarayev, Richard G. Cliff, Simardeep Maangat
Publikováno v:
CICC
A wide-range transceiver was designed and fabricated in a 90-nm TSMC CMOS logic process. Each transceiver channel contains a transmitter and receiver with clock data recovery (CDR) circuit. The range of operation for this transceiver is from 622 Mbps
Publikováno v:
CICC
This paper embodies a methodology used to create high-speed transceiver behavior models employed within a signal integrity-based link simulation platform. This tool includes routines for the optimization of transmitter pre-emphasis and equalization.
Autor:
Jim Park, Michael D. Hutton, Bruce B. Pedersen, Vinson Chan, Sergey Shumarayev, Jay Schleicher, Rakesh H. Patel, Tony Ngai, Peter J. Kazarian, Victor Maruri
Publikováno v:
FPGA
As programmable logic grows more viable for implementing full design systems, performance has become a primary issue for programmable logic device architectures. This paper presents the high-level design of Dali, a PLD architecture specifically aimed