Zobrazeno 1 - 10
of 42
pro vyhledávání: '"Sergei Kostin"'
Publikováno v:
Journal of Obstetrics and Gynaecology Canada. 42:953-956
Objective To investigate the rates of intrauterine adhesion following hysteroscopy for removal of RPOC associated with surgical termination of pregnancy. Methods We conducted a retrospective cohort study of all cases of removal by hysteroscopy of RPO
Publikováno v:
PATMOS
2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
The conventional design techniques struggle with integration density and constantly strengthening requirements of today's nanometer technology. Timing-critical paths analysis is one of such tasks. It has applications in critical path identification,
Publikováno v:
"2018 25th International Conference ""Mixed Design of Integrated Circuits and System"" (MIXDES)"
"""2018 25th International Conference """"Mixed Design of Integrated Circuits and System"""" (MIXDES)"""
MIXDES
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES)
"""2018 25th International Conference """"Mixed Design of Integrated Circuits and System"""" (MIXDES)"""
MIXDES
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES)
In this paper we present a very fast fault simulation method for sequential circuits, which is based on accommodation of exact parallel critical path tracing in combinational circuits for using it also in case of sequential circuits. Formulas are dev
This book contains extended and revised versions of the best papers presented at the 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, held in Tallinn, Estonia, in September 2016. The 11 papers included
Publikováno v:
IFIP Advances in Information and Communication Technology ISBN: 9783319671031
VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability
VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9cf5cc3cc71fd2a268b7dd77315b5f24
https://doi.org/10.1007/978-3-319-67104-8
https://doi.org/10.1007/978-3-319-67104-8
Publikováno v:
2016 11th European Workshop on Microelectronics Education (EWME)
EWME
EWME
We propose a tool set for teaching and e-learning the main principles of design-for-testability technics for digital systems. It is a collection of software tools which simulate a circuit under test, emulate a pool of different strategies, methods an
Autor:
Leticia Bolzani Poehls, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Raimund Ubar, Thiago Santos Copetti, Fabian Vargas, Guilherme Cardoso Medeiros
Publikováno v:
2016 17th Latin-American Test Symposium (LATS)
LATS
LATS
Continuous technology scaling poses reliability concerns that directly affect the Integrated Circuit's (IC) lifespan. One of the most important issues in nanoscale circuits is related to the time-dependent variation caused by Negative Bias Temperatur
Publikováno v:
2016 IEEE Nordic Circuits and Systems Conference (NORCAS)
NORCAS
NORCAS
The importance of diagnostic test generation cannot be overemphasized as it is increasingly becoming important for diagnosing the complex circuits designed today. One approach is to use a test set that is generated originally for testing as the start
Autor:
Raimund Ubar, Marco Gaudesi, Valentin Tihhomirov, Leticia Bolzani Poehls, Guilherme Cardoso Medeiros, Sergei Kostin, Matteo Sonza Reorda, Maksim Jenihhin, Giovanni Squillero, Jaan Raik, Thiago Santos Copetti, Fabian Vargas
Publikováno v:
Journal of Electronic Testing
The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths betw
Publikováno v:
Microprocessors and Microsystems. 32:279-287
This paper presents an optimized fault diagnosing procedure applicable in Built-in Self-Test environments. Instead of the known approach based on a simple bisection of patterns in pseudorandom test sequences, we propose a novel bisection procedure wh