Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Seoung-Ju Chung"'
Autor:
Ki-Seon Park, Tsuneo Inaba, Hiromi Noro, Jonghoon Oh, Sung-Woong Chung, Akihito Yamamoto, Hyeongon Kim, Hisato Oyamatsu, Kazumasa Sunouchi, Jinwon Park, Yutaka Shirai, Seoung-Ju Chung, Dong-Keun Kim, Kenji Tsuchida, Ji-Hyae Bae, Hyunin Moon, Kwang-Myoung Rho
Publikováno v:
ISSCC
Spin-transfer torque magnetic RAM (STT-MRAM) is one of the most promising nonvolatile memories with guaranteed high-speed read and write operations. Along with performance improvements in the tunnel magnetoresistance (TMR) and the magnetic tunnel jun
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f5e7dd5fe478f795d6d980cb7a53276
https://doi.org/10.1109/isscc.2017.7870428
https://doi.org/10.1109/isscc.2017.7870428
Autor:
Suock Chung, J. H. Lee, W. S. Nam, Janice H. Nickel, Hyunsang Hwang, Junkyo Suh, Kee-jeung Lee, Kwang-Ok Kim, Y. K. Kim, R.S. Williams, Yong Soo Kim, K. M. Rho, Ho-Seok Lee, Hyejung Choi, Sung Kye Park, H. S. Shin, K. Cho, J. T. Cheong, S. N. Park, S. Chae, Juyeab Lee, Kwon Hong, Sook-Joo Kim, Jianhua Yang, Seoung-Ju Chung, Seung Hwan Lee, Hyung Dong Lee, H. G. Jeong, C. G. Lee, Y. S. Sohn, Hyeon-Koo Cho, E.-R. Hwang, Frederick A. Perner, Sung-Joo Hong, Jumsoo Kim
Publikováno v:
2012 Symposium on VLSI Technology (VLSIT).
4F2 selector-less crossbar array 2Mb ReRAM test chip with 54nm technology has been successfully integrated for high cell efficiency and high density memory applications by implementing parts of decoders to row/column lines directly under the cell are
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::618e8463285d552f2fac1c10f5605127
https://doi.org/10.1109/vlsit.2012.6242506
https://doi.org/10.1109/vlsit.2012.6242506
Autor:
Joong-Sik Kim, Seoung-Ju Chung, Greg Popov, Michael A. Van Buskirk, Sung-Woong Chung, Seung Hwan Lee, Sang-Min Hwang, Donghee Son, Sung-Joo Hong, Srinivasa Banna, Sungwook Park, Sang-Hoon Cho, Sunil Bhardwaj, Venkatesh P. Gopinath, Jae-Sung Roh, Jungtae Kwon, David Kim, Mayank Gupta, Tae-Su Jang
Publikováno v:
2010 Symposium on VLSI Technology.
Vertical double gate floating body (FB) Z-RAM memory cell technology fabricated on a recess gate DRAM technology is presented. Cell operating voltage of 0.5V with comparable static retention and > 1000x improvement in dynamic retention is reported. T
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7634da74d2509370f83651735ea79ec3
https://doi.org/10.1109/vlsit.2010.5556212
https://doi.org/10.1109/vlsit.2010.5556212
Autor:
Tae-Su Jang, Joong-Sik Kim, Sang-Min Hwang, Young-Hoon Oh, Kwang-Myung Rho, Seoung-Ju Chung, Su-Ock Chung, Jae-Geun Oh, Bhardwaj, S., Jungtae Kwon, Kim, D., Nagoga, M., Yong-Taik Kim, Seon-Yong Cha, Seung-Chan Moon, Sung-Woong Chung, Sung-Joo Hong, Sung-Wook Park
Publikováno v:
2009 Symposium on VLSI Technology; 2009, p234-235, 2p