Zobrazeno 1 - 10
of 84
pro vyhledávání: '"Seongmoon Wang"'
Autor:
Xiangyu Tang, Seongmoon Wang
Publikováno v:
IEEE Transactions on Computers. 59:1309-1319
A self-diagnosis circuit that can be used for built-in self-repair is proposed. The circuit under diagnosis is assumed to be composed of a large number of field repairable units (FRUs), which can be replaced with spares when they are found to be defe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::812bd85ea8720fe946ddadfca9c9404c
https://doi.org/10.1109/tc.2009.182
https://doi.org/10.1109/tc.2009.182
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18:1672-1685
This paper presents a test data compression scheme that can be used to further improve compressions achieved by linear-feedback shift register (LFSR) reseeding. The proposed compression technique can be implemented with very low hardware overhead. Th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0c7c284432b5c8a52426e6d9f469e9ac
https://doi.org/10.1109/tvlsi.2009.2026420
https://doi.org/10.1109/tvlsi.2009.2026420
Autor:
Wenlong Wei, Seongmoon Wang
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27:2039-2052
This paper presents an efficient method to block unknowns for temporal compactors. The proposed blocking logic can reduce data volume required to control the blocking logic and increase the number of scan cells that are observed by temporal compactor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ac9cfcde5d51cdb894a060ce0c913503
https://doi.org/10.1109/tcad.2008.2006093
https://doi.org/10.1109/tcad.2008.2006093
Publikováno v:
IEEE Transactions on Computers. 57:978-989
This paper presents an efficient method to block unknown values for temporal compactors. The control signals for the blocking logic are generated by a linear feedback shift register (LFSR). Control patterns, which describe values required at the cont
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c70ddef86ab27ba3aed9355f61617749
https://doi.org/10.1109/tc.2007.70833
https://doi.org/10.1109/tc.2007.70833
Autor:
Seongmoon Wang
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 15:777-789
This paper presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a2bc1fcb53d2ac8b39776ceaa31bd96e
https://doi.org/10.1109/tvlsi.2007.899234
https://doi.org/10.1109/tvlsi.2007.899234
Autor:
Seongmoon Wang, Sandeep K. S. Gupta
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25:1565-1574
A new built-in self-test (BIST) test pattern generator (TPG) design, called low-transition random TPG (LT-RTPG), is presented. An LT-RTPG is composed of a linear feedback shift register (LFSR), a /spl kappa/-input AND gate, and a T flip-flop. When us
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::85359b22bd3d47607a67d214d125b831
https://doi.org/10.1109/tcad.2005.855927
https://doi.org/10.1109/tcad.2005.855927
Autor:
Sandeep K. S. Gupta, Seongmoon Wang
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21:954-968
An automatic test pattern generation (ATPG) technique is proposed that reduces switching activity during testing of sequential circuits that have full scan. The objective is to permit safe and inexpensive testing of low-power circuits and bare dies t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::864df074488a58dfecf68495c353f9ef
https://doi.org/10.1109/tcad.2002.800460
https://doi.org/10.1109/tcad.2002.800460
Autor:
Seongmoon Wang
Publikováno v:
VTS
In this paper, a cost efficient test methodology to screen chips that have resistive open defects under the presence of process variation is proposed. The proposed test methodology is based on small delay defect testing. The entire test session is di
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::81c66e9d55b1285a82e242b5571e5b2c
https://doi.org/10.1109/vts.2011.5783771
https://doi.org/10.1109/vts.2011.5783771
Autor:
Xiaoqing Wen, Seongmoon Wang
Publikováno v:
Power-Aware Testing and Test Strategies for Low Power Devices ISBN: 9781441909275
Test pattern generation is an important part of the VLSI testing flow that offers many possibilities that can be explored for reducing test power dissipation. The issue of test power reduction can be addressed at various stages of test generation for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eadedb29d2f42aacb9e9c02da59d75ba
https://doi.org/10.1007/978-1-4419-0928-2_3
https://doi.org/10.1007/978-1-4419-0928-2_3
Autor:
Xiangyu Tang, Seongmoon Wang
Publikováno v:
DSN
A self-diagnosis circuit that can be used for builtin self-repair is proposed. The circuit under diagnosis is assumed to be comprised of a large number of field repairable units (FRUs), which can be replaced with spares when they are found to be defe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1ec6ae19c176bed0bb02b70183a5a11b
https://doi.org/10.1109/dsn.2009.5270327
https://doi.org/10.1109/dsn.2009.5270327