Zobrazeno 1 - 10
of 23
pro vyhledávání: '"Seong-Yeol Mun"'
Autor:
Srikanth Samavedam, Hsien-Ching Lo, Shashidhar Shintri, Jianwei Peng, Seong Yeol Mun, Seng Nguon Ting, Ma Wei, El Mehdi Bazizi, C. Gaire, James Chen, Edward Reis, Baofu Zhu, Qi Yi, Owen Hu
Publikováno v:
IEEE Transactions on Electron Devices. 65:3640-3645
We present a novel method to form the source/ drain (S/D) cavity for pFET performance improvement—we named this cavity as doping-assisted cavity as its profile is controlled by the lightly doped drain implantation. By utilizing the enhanced etch ra
Autor:
Yue Hu, Alina Vinslava, X. Zhang, Pei Zhao, Srikanth Samavedam, Owen Hu, Jianwei Peng, Seong Yeol Mun, Hsien-Ching Lo, Qi Yi, Yan Ping Shen, Yong Jun Shi, Yanzhen Wang, Dongil Choi, Ashish Kumar Jha, Zang Hui, Jae Gon Lee, Dou Xinyuan, Hong Wei, El Mehdi Bazizi
Publikováno v:
2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
We present a novel cavity engineering work – we named this cavity as dual-curvature cavity, which improves pFET electrical performance. This new cavity shape design minimizes the source/drain leakage penalty from deeper cavity depth while enabling
Autor:
Seong Yeol Mun, Hong Yu, J. Versaggi, H. Wei, Alina Vinslava, C. Kyono, Jianwei Peng, Yue Hu, Hui Zhan, Xiaoli He, W.H. Chen, Yanzhen Wang, Baofu Zhu, Mitsuhiro Togo, Qi Yi, X. Zhang, M. Mohan, E. Lavigne, Owen Hu, Srikanth Samavedam, X. Dou, Jae Gon Lee, Dongil Choi, A. Sirman, Jinping Liu, D. K. Sohn, D. Kang, Ashish Kumar Jha, C. Gaire, Shi Yongjun, Zang Hui, Shen Yanping, Hsien-Ching Lo, Chloe Yong, X. Wan, Pei Zhao, D. Zhou
Publikováno v:
2018 IEEE Symposium on VLSI Technology.
We present a state-of-art 12LP FinFET technology with PPA (Performance, Power, and Area) improvement over 14LPP. 12LP enables >10% area reduction including a 7.5T library and 16% power reduction at fixed frequency or a 15% performance improvement at
Autor:
B. Liu, J. Cho, Srikanth Samavedam, Seong Yeol Mun, Shi Yongjun, Jae Gon Lee, J. Ciavatti, V. Mahajan, Hong Wei, Baofu Zhu, D. K. Sohn, Wong Chun Yu, T. J. Lee, Pratik Agnihotri
Publikováno v:
2018 IEEE International Conference on Microelectronic Test Structures (ICMTS).
The quantitative model of effective total capacitance, Ceff, of a CMOS ring oscillator (R/O) inverter chain in a 14nm node FinFET 3D structure using advanced Replacement Metal Gate (RMG) is successfully extracted using all the unit capacitance compon
Publikováno v:
The Journal of the Korea institute of electronic communication sciences. 9:1227-1232
본 논문은 기존의 poly length만의 축소와 달리 입, 출력 소자를 포함한 core 디바이스의 0.13㎛ 디자인을 10% 축소하는 것으로 여러 채널 길이에 따른 body effect와 doping profile simulation을 해석하였다
Publikováno v:
The Journal of the Korea institute of electronic communication sciences. 9:847-852
반도체 소자 제조에서 비용 절감을 위한 공정기술의 스케일링 가속화 경향에 따라 축소기술에 대한 요구가 증가되고 있다. 축소에 따른 또 다른 가장 큰 문제점의 하나는 Hot Carrier Injection (H
Publikováno v:
The Journal of the Korea institute of electronic communication sciences. 9:747-752
본 논문은 0.13㎛ 기술의 디자인을 10% 축소하는데 기존의 로직 디바이스만의 축소와는 달리 로직뿐 아니라 입, 출력 회로의 축소에 관한 것이다. 게이트 산화막(1.2V)을 decoupled plasma nitridation(D
Publikováno v:
Journal of information and communication convergence engineering. 11:288-292
In this paper, a carbon implant is investigated in detail from the perspectives of performance advantages and side effects for the thick n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET). Threshold voltage (Vth) adjustment using a c
Autor:
Seong-Yeol Mun, Shesh Mani Pandey, Xusheng Wu, Manfred Eller, Sri Samavedam, Sanjay Parihar, David Burnett
Publikováno v:
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
The basic multi-gate Vt variation model for uniform doping is extended to support a 2-region fin doping methodology that provides good agreement with Vt mismatch measurements as well as useful insights into how the non-uniform fin doping impacts the
Publikováno v:
The Journal of the Korean Institute of Information and Communication Engineering. 16:2525-2531
Al-Cu alloy has been used as a circuit material for its low resistance and ease to process for long years at CMOS technology. However, basically metal is very susceptible to corrosion and which has been a long pending trouble in various fields using