Zobrazeno 1 - 8
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pro vyhledávání: '"Seong-I Lei"'
Autor:
Seong-I Lei, 李尚貽
96
With the advanced VLSI technology, sharp slew rate and low power comsumption are often required in integrated circuit design. Timing buffering on non-critical nets may result in extra power dissipation and waste of buffering resource. Unfortu
With the advanced VLSI technology, sharp slew rate and low power comsumption are often required in integrated circuit design. Timing buffering on non-critical nets may result in extra power dissipation and waste of buffering resource. Unfortu
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/70513903768974191690
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36:1103-1112
Threshold voltage assignment is a very effective technique to reduce leakage power consumption in modern integrated circuit design. As feature size continues to decrease, the layout constraints [called minimum implant area (MinIA) constraints] on the
Autor:
Seong-I Lei, Wai-Kei Mak
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35:246-259
Pin assignment and escape routing are two closely related problems and it is desired to consider routability during pin assignment for package-board co-design. During pin assignment and escape routing, differential pairs and blind-via usage are two m
Autor:
Seong-I Lei, Wai-Kei Mak
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32:1866-1878
With the increasing complexity of circuit design in recent years, the pin assignment and escape routing problems for field-programmable gate array (FPGA) on a printed circuit board (PCB) have become greatly difficult due to the fast increase in pin c
Publikováno v:
ASP-DAC
Threshold voltage assignment is a very effective technique to reduce leakage power consumption in modern integrated circuit (IC) design. As feature size continues to decrease, the layout constraints (called MinIA constraints) on the implant area, whi
Publikováno v:
ISQED
Double patterning lithography (DPL) for 32nm and 22nm technology nodes requires decomposing a layout into two masks for lithography. It is important to consider DPL during the detailed routing stage so that the layout can be decomposed easily with th
Autor:
Wai-Kei Mak, Seong-I Lei
Publikováno v:
FPL
With the increasing complexity of circuit design in recent years, the pin assignment and escape routing problems for FPGA on a PCB have become greatly difficult due to the fast increase in pin count and density. Most existing works only focus on eith
Autor:
Seong-I Lei, Wai-Kei Mak
Publikováno v:
2011 International Conference on Field Programmable Logic & Applications (FPL); 2011, p435-440, 6p