Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Seok-Hun Hyun"'
Autor:
Jongwook Park, Jung-Hwan Choi, Seung-Jun Bae, Si-Hyeong Cho, Seunseob Lee, Young-Ryeol Choi, In-Dal Song, Kwang-Il Park, Ki-Ho Kim, Jin-Seok Heo, Young-Soo Sohn, Dong-Hun Lee, Eunsung Seo, Junha Lee, Gil-Hoon Cha, Hyuck-Joon Kwon, Jin-Hyeok Baek, Daesik Moon, Youn-sik Park, Kyung-Soo Ha, Chang-Kyo Lee, Seok-Hun Hyun, Seong-Jin Jang
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:2906-2916
This paper presents a dual-loop two-step ZQ calibration scheme with a 20-nm DRAM process to support dedicated supply voltages ( $V_{DD}$ and $V_{DDQ}$ ). The proposed calibration scheme improves system signal integrity by maintaining the targeted out
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::357e219db9060554f370c477b6da0d04
https://doi.org/10.1109/jssc.2018.2850937
https://doi.org/10.1109/jssc.2018.2850937
Autor:
Jae-Yoon Sim, Il-Min Yi, Seong-Jin Jang, Jung-Hwan Choi, Min-Kyun Chae, Hong-June Park, Byungsub Kim, Seok-Hun Hyun, Seung-Jun Bae
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:144-154
A time-based (TB) receiver (RX) with a 2-tap TB decision feedback equalizer (DFE) is proposed for mobile DRAM interface. The TB RX consists of a voltage-to-time converter (VTC), a TB DFE, and a time comparator. The VTC converts the RX input voltage t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f3a32e78941e2538965600b9d1b057d6
https://doi.org/10.1109/jssc.2017.2746698
https://doi.org/10.1109/jssc.2017.2746698
Autor:
Daesik Moon, Jung-Hwan Choi, Seok-Hun Hyun, Jung-Bae Lee, Sung-Woo Yoon, Su-Jin Park, Dong-Hoon Lee, Jin-Hyeok Baek, Seung-Jun Bae, Y.S. Park, Hui-Kap Yang, Ki-Han Kim, Hyuck-Joon Kwon, Young-Soo Sohn, Chang-Kyo Lee, Bok-Gue Park, Young-Jae Kim, Jin-Seok Heo, Kyungryun Kim, Soobong Jang, Ki-Ho Kim, Joung-Wook Moon, Kwang-Il Park, Jae-Hyung Lee
Publikováno v:
VLSI Circuits
A 5Gb/s/pin 16Gb LPDDR4/4X reconfigurable SDRAM with a self-mode detection scheme, a voltage-high keeper (VHK) for un-terminated load and a prediction-based fast-tracking ZQ algorithm is implemented in 10nm class ($2^{nd}$ generation) DRAM process. P
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3570d22e6ced3e4156d6ecfd888ad57d
https://doi.org/10.23919/vlsic.2019.8778102
https://doi.org/10.23919/vlsic.2019.8778102
Autor:
Soo-bong Chang, Young-Soo Sohn, Hyuck-Joon Kwon, Duk-ha Park, Hyong-Ryol Hwang, Junghwan Park, Kwang-II Park, Choi Yeon-Kyu, Young Hoon Son, Hyunyoon Cho, Byongwook Na, Hyung-Joon Chi, Lim Suk-Hyun, Jin-Hun Jang, Tae-Young Oh, Seung-Jun Shin, Seouk-Kyu Choi, Daesik Moon, Kim Sang-Yun, Ki-Won Park, Seong-Jin Jang, Hyo-Joo Ahn, Jung-Hwan Choi, Seungseob Lee, Chang-Kyo Lee, Dongkeon Lee, Young-Hwa Kim, Youn-sik Park, Kyung-Soo Ha, Seok-Hun Hyun
Publikováno v:
ISSCC
High-speed and low-power techniques for the latest mobile DRAMs, such as LPDDR4/4X [1–3], have been developed to enable high-resolution displays, multiple cameras and 4G communication in mobile devices. However, DRAM with higher bandwidth and lower
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3f8b77e89febd51cb1428fa3986dea1f
https://doi.org/10.1109/isscc.2019.8662509
https://doi.org/10.1109/isscc.2019.8662509
Autor:
Young-Soo Sohn, Joung-Wook Moon, Dong-Hun Lee, Haeyoung Chung, Seok-Yong Kang, Seong-Jin Jang, Jun-Bae Kim, Yong-Ho Cho, Ki-Ho Kim, In-Dal Song, Kwang-Il Park, Hundai Choi, Jung-Hwan Choi, Hye-Sung Yoo, Seok-Hun Hyun, Il-Won Park, Ki-Jae Song
Publikováno v:
A-SSCC
This paper presents a wide-frequency-range, self-calibrating, built-off-test (BOT) transceiver for a DDR4 SDRAM interface. The proposed BOT transceiver consists of a data transceiver, a phase-locked loop, a delay-locked loop, a self-timing calibratio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c643084e66fe95f71eb2fcf04a50c308
https://doi.org/10.1109/asscc.2018.8579329
https://doi.org/10.1109/asscc.2018.8579329
Autor:
Jung-Hwan Choi, In-Dal Song, Jin-Oh Ahn, Kwang-Il Park, Daesik Moon, Dong-Ju Kim, Kyung-Soo Kim, Jin-Seok Heo, Seung-Jun Bae, Seokhong Kwon, Young-Soo Sohn, Jin-Hyeok Baek, Jongmin Kim, Byung-Cheol Kim, Hyuck-Joon Kwon, Chang-Kyo Lee, Seong-Jin Jang, Jeonghyeon Cho, Min-Su Ahn, Jeong-Sik Nam, Ilgweon Kim, Seok-Hun Hyun, Jeong-Hoon Oh, Gil-Hoon Cha, Jae-Joon Song, Ki-Ho Kim
Publikováno v:
VLSI Circuits
A sub-0.85V, 6.4Gb/s TX-interleaved transceiver with fast wake-up time using 2-step charging control and a V OH calibration scheme is implemented using 20nm DRAM process. Adopting an interleaving scheme based on improved DRAM process, the proposed de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d55ad90ea415991e854486a0366baf5f
https://doi.org/10.1109/vlsic.2018.8502299
https://doi.org/10.1109/vlsic.2018.8502299
Autor:
Seung-Jun Bae, Jongwook Park, Young-Soo Sohn, Taesung Kim, Sewon Eom, Young-Seok Kim, Hyuck-Joon Kwon, Daesik Moon, Seong-Hwan Kim, Ki-Ho Kim, Seungseob Lee, Eungsung Seo, Jin-Hyeok Baek, Yoon-Joo Eom, Kyoung-Ho Kim, Jung-Hwan Choi, Tae-Young Oh, Gil-Hoon Cha, Seok-Hun Hyun, Yoon-Gyu Song, Youn-sik Park, Kyung-Soo Ha, Young Hoon Son, Dae-Hee Jung, In-Dal Song, Kwang-Il Park, Hyunyoon Cho, Bo-Tak Lim, Chang-Kyo Lee, Si-Hyeong Cho, Joon-Young Park, Junha Lee, Jin-Seok Heo, Young-Ryeol Choi, Seong-Jin Jang
Publikováno v:
A-SSCC
This paper presents a dual-loop 2-step ZQ calibration scheme with 20nm DRAM process to support dedicated supply voltage (VDD, VDDQ). The proposed calibration scheme maintains a target value of on-die termination (ODT) in DQ/CA regardless of the suppl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49e6cc5f556a1c86f0e956ef3176bfec
https://doi.org/10.1109/asscc.2017.8240239
https://doi.org/10.1109/asscc.2017.8240239
Autor:
Seong-Jin Jang, Byungsub Kim, Jung-Hwan Choi, Min-Kyun Chae, Hong-June Park, Seung-Jun Bae, Il-Min Yi, Jae-Yoon Sim, Seok-Hun Hyun
Publikováno v:
ISSCC
Single-ended transceivers are mostly used for DRAM interfaces to reduce pin count. A low-supply transceiver is preferred, especially for mobile DRAM interfaces, for low-power consumption while maintaining a high-speed interface for transmission of im
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::905fb9388911829ea1430fcebd93ab74
https://doi.org/10.1109/isscc.2017.7870430
https://doi.org/10.1109/isscc.2017.7870430
Autor:
Hyo-Joo Ahn, Jae-Young Lee, Yoon-Joo Eom, Seok-Hun Hyun, Junha Lee, Kyoung-Ho Kim, Jong-Min Bang, Yong-Cheol Bae, Hye-Ran Kim, Hoon Lee, Jong-Hyuk Kim, Joon-Young Park, Seung-Jun Shin, Ki-Han Kim, Tae-Young Oh, Hanna Park, Hyuck-Joon Kwon, Young-Ryeol Choi, Yoon-Hwan Yoon, In-Dal Song, Youn-sik Park, Su-Jin Park, Soo-bong Chang, Kwang-Il Park, Kyong-Ho Jeon, Jin-Hee Park, Jung-Sik Kim, Chang-Kyo Lee, Young Sang Choi, Yoon-Gyu Song, Hyong-Ryol Hwang, Du-Yeul Kim, Gyo-Young Jin, Ho-Jun Chang, Seong-Jin Jang, Jung-Hwan Choi, Seung-Jun Bae
Publikováno v:
ISSCC
With growing demand for low-power mobile applications, such as wearable devices, smart phones and tablet PCs, low-power mobile DRAM has been identified as a mandatory requirement for low-power system designs. The recently developed LPDDR4 [1] is stil
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a79ff3e9fad79cc10a0cc95dfe6531e7
https://doi.org/10.1109/isscc.2017.7870425
https://doi.org/10.1109/isscc.2017.7870425
Autor:
Kwang-Hyun Lee, Sung-dong Suh, Seong-Gu Kim, Sang-Hoon Choi, Jinyong Choi, Beom-Seok Lee, Dong-Jae Shin, Jeong-Kyoum Kim, Hong-gu Yoon, Hyukjoon Kwon, Sangdeok Han, Junghyung Pyo, Jeong-Sik Nam, Jung-Hwan Choi, Joo-Sun Choi, Kyoung-won Na, In-sung Joe, Yoon-dong Park, Kyoung-ho Ha, Ho-Cheol Lee, Seok-Hun Hyun, Taejin Jeong, Ho-Chul Ji, Chilhee Chung, Jung-hye Kim, Sunjoong Kim, Ki-Ho Kim, Yong-hwack Shin, Kwan-Sik Cho, Seokyong Hong, Hyunil Byun
Publikováno v:
10th International Conference on Group IV Photonics.
Optical interconnect for a DDR3 DRAM device is verified at a 4:1-serialized 1.6-Gbps data rate using a FPGA-based memory controller board and optical transceiver chips with bulk-Si-based photonic die and electronic die co-packaged.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7087a13bf76ed4a85747ceaae3ebacb0
https://doi.org/10.1109/group4.2013.6644462
https://doi.org/10.1109/group4.2013.6644462