Zobrazeno 1 - 10
of 27
pro vyhledávání: '"Seiyang Yang"'
Autor:
Seiyang Yang
Publikováno v:
KIPS Transactions on Computer and Communication Systems. 5:439-446
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::997dbf17529586bb45b9bbc07d0e8a53
https://doi.org/10.3745/ktccs.2016.5.12.439
https://doi.org/10.3745/ktccs.2016.5.12.439
Autor:
Seiyang Yang, Doohwan Kwak
Publikováno v:
KIPS Transactions on Computer and Communication Systems. 4:147-152
In general, there are two synchronization methods in parallel event-driven simulation, pessimistic approach and optimistic approach. In this paper, we propose a new approach, sporadic synchronization combining both for prediction-based parallel event
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::777625544f13cb254a870d1607af1db5
https://doi.org/10.3745/ktccs.2015.4.5.147
https://doi.org/10.3745/ktccs.2015.4.5.147
Autor:
Seiyang Yang, Jaehoon Han
Publikováno v:
World Congress on Electrical Engineering and Computer Systems and Science.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::14304246d286ae9d63f090f5620bc27b
https://doi.org/10.11159/eee17.103
https://doi.org/10.11159/eee17.103
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32:845-857
Multilevel temporal-parallel event-driven simulation is a new radically different approach to simulation of designs described in Verilog HDL. It is based on a concept of time-parallel simulation applied to gate-level timing simulation. The simulation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2f82bcecab96b25554132f4a21767fbe
https://doi.org/10.1109/tcad.2013.2237769
https://doi.org/10.1109/tcad.2013.2237769
Publikováno v:
The KIPS Transactions:PartA. :141-146
In this paper, we proposed an efficient FPGA-based simulation acceleration method based on FPGA compilation avoidance, which can effectively decrease the long debugging turnaround time incurred from the every debugging process in the functional verif
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::106a500ca8a0db8ed0f413eda0014bec
https://doi.org/10.3745/kipsta.2007.14-a.3.141
https://doi.org/10.3745/kipsta.2007.14-a.3.141
Publikováno v:
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8606537891bc78bc9cc3762e630a23b8
https://doi.org/10.7873/date.2014.329
https://doi.org/10.7873/date.2014.329
Publikováno v:
Conference Proceedings on 3rd Annual International Conference on Advances in Distributed and Parallel Computing.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::20983debe0b1f9694848584cce5df5cf
https://doi.org/10.5176/2251-1652_adpc12.04
https://doi.org/10.5176/2251-1652_adpc12.04
Publikováno v:
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).
Multi-core processors have become common in current computing platforms. Today, most of multi-core workstations and PCs have adopted NUMA (Non-Uniform Memory Access) advanced memory architecture for high performance and scalability. In response, EDA
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2e60aee1861c86d4f5c1be621b3ac75c
https://doi.org/10.1109/smacd.2012.6339456
https://doi.org/10.1109/smacd.2012.6339456
Publikováno v:
DATE
Simulation speedup offered by distributed parallel event-driven simulation is known to be seriously limited by the synchronization and communication overhead. These limiting factors are particularly severe in gate-level timing simulation. This paper
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1b25a189bcecb3007fdc6eb5ee75101f
https://doi.org/10.1109/date.2011.5763251
https://doi.org/10.1109/date.2011.5763251
Publikováno v:
DATE
This paper describes a new and efficient solution to a distributed event-driven gate-level HDL simulation. It is based on a novel concept of spatial parallelism using accurate prediction of input and output signals of individual local modules in loca
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::30bb03dc1586f9a9b739794ea6a1cfd2
https://doi.org/10.1109/date.2011.5763280
https://doi.org/10.1109/date.2011.5763280