Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Sean M. Seutter"'
Materials Technology Co-Optimization of Self-Aligned Gate Contact for Advanced CMOS Technology Nodes
Autor:
Keyvan Kashefizadeh, Nancy Fung, T. E. Sato, Nitin K. Ingle, W. Xu, W. Lei, Benjamin Colombeau, Anchuan Wang, Yu Lei, Ajay Bhatnagar, Ashish Pal, P. Wang, Sanjay Natarajan, D. Cui, Angada B. Sachid, Avgerinos V. Gelatos, Blessy Alexander, C. Lee, B. Brown, D. Hwang, Sean M. Seutter, K. Mikhaylichenko, T. H. Ha, M. Kawasaki, Yi Xu, Buvna Ayyagari, J. Ferrell, M. Cogorno, El Mehdi Bazizi, T. Luu
Publikováno v:
2020 IEEE Symposium on VLSI Technology.
Materials technology co-optimization (MTCO) modeling is used for the first time to simulate Performance-Power-Area (PPA) benefits of self-aligned gate contact (SAGC) technology. We also demonstrate a process flow to integrate novel CMOS compatible ma
Autor:
R. Hung, Nihit Chattar, Souvik Mahapatra, Sean M. Seutter, Christopher S. Olsen, C. Sandhya, Juzer Vasi, Udayan Ganguly, L. Date, Apoorva B Oak
Publikováno v:
IndraStra Global.
Program/Erase (P/E) cycling endurance in poly-Si/Al(2)O(3)/SiN/SiO(2)/Si (SANOS) memories is systematically studied. Cycling-induced trap generation, memory window (MW) closure, and eventual stack breakdown are shown to be strongly influenced by the
Autor:
Suddhasatta Mahapatra, Sean M. Seutter, Christopher S. Olsen, R. Hung, L. Date, B. Apoorva, Juzer Vasi, Udayan Ganguly, C. Sandhya
Publikováno v:
2009 2nd International Workshop on Electron Devices and Semiconductor Technology.
Composition of the silicon-nitride charge trap layer strongly impacts electron and hole trap properties. This significantly impacts charge trap flash memory performance and reliability. Important trade-offs between Program/Erase (P/E) levels (memory
Autor:
R. Hung, Sean M. Seutter, Christopher S. Olsen, L. Date, Udayan Ganguly, Souvik Mahapatra, C. Sandhya, N. Chattar, Juzer Vasi
Publikováno v:
IndraStra Global.
Silicon-nitride trap layer stoichiometry in charge trap flash (CTF) memory strongly impacts electron and hole trap properties, memory performance, and reliability. Important tradeoffs between program/erase (P/E) levels (memory window), P- and E-state
Autor:
Udayan Ganguly, Sean M. Seutter, R. Hung, Souvik Mahapatra, N. Chattar, L. Date, C. Sandhya, A.B. Oak, Christopher S. Olsen, A.S. Joshi, Juzer Vasi
Publikováno v:
IndraStra Global.
Despite significant advances in structure and material optimization, poor erase (E) speeds and high retention charge loss remain the challenging issues for charge trap Flash (CTF) memories. In this paper, the dependence of SANOS memory performance an
Autor:
Khaled Ahmed, Nety M. Krishna, Christopher S. Olsen, Sean M. Seutter, Souvik Mahapatra, G. Conti, Udayan Ganguly, Kaushal K. Singh, C. Sandhya, Juzer Vasi
Publikováno v:
2008 15th International Symposium on the Physical and Failure Analysis of Integrated Circuits.
The effect of nitride composition, i.e. Si-rich (Si+) and N-rich (N+) nitride bi-layers separated by an oxynitride (SiON) layer on memory performance and reliability is studied. Bottom Si+ layer and top N+ forms the Si+/N+ bi-layer that is compared t
Autor:
Kangzhan Zhang, Chung-Hu Ge, Kenneth Wu, C.H. Ko, C.N. Ye, T.M. Kuan, Wen-Chin Lee, Hung-Wei Chen, Sean M. Seutter, Chun-Yu Wu, G. Tsai, T.J. Wang
Publikováno v:
2008 Symposium on VLSI Technology.
State-of-the-art low-K spacer technology featuring novel CVD-SiBCN material is demonstrated for the first time. A significant 20% CMOS ring speed enhancement is demonstrated with SiBCN (K=5.2) spacer, compared to Si3N4 (K=7.5) spacer, due to reduced
Autor:
Sean M. Seutter, Christopher S. Olsen, Khaled Ahmed, P.K. Singh, Udayan Ganguly, Souvik Mahapatra, G. Conti, Kaushal K. Singh, R. Hung, C. Sandhya, Juzer Vasi, Nety M. Krishna
Publikováno v:
2008 IEEE International Reliability Physics Symposium.
The performance and reliability of charge trap flash with single and bi-layer Si-rich and N-rich nitride as the storage node is studied. Single layer devices show lower memory window and poor cycling endurance, and the underlying physical mechanisms
Publikováno v:
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures. 23:2340
Less than 10% pattern-dependent microloading and greater than 95% step coverage are required for low temperature deposition of Si3N4 spacer and etch stop films in advanced logic and dynamic random access memory semiconductor applications. A single-wa
Thermal Chemical Vapor Deposition of Bis(Tertiary-Butylamino)Silane-based Silicon Nitride Thin Films
Publikováno v:
Journal of The Electrochemical Society. 152:G316
Sub-90 nm device design presents challenges for lowering thermal budget as well as depositing uniform and conformal thin films for front-end-of-line silicon nitride applications. Among other low-temperature precursors forsilicon nitride film depositi