Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Scott R. Stiffler"'
Publikováno v:
Optical Microlithography XXXI.
Manufacturing embedded DRAM deep trench capacitors can involve etching very deep holes into silicon wafers1. Due to various design constraints, these holes may not be uniformly distributed across the wafer surface. Some wafer processing steps for the
Autor:
Noah Zamdmer, Paul C. Parries, Scott R. Stiffler, S. Lee, K. McStay, Ravikumar Ramachandran, W. K. Henson, C. Ortolland, G. La Rosa, K. M. Boyd
Publikováno v:
IBM Journal of Research and Development. 62:11:1-11:7
A highly optimized silicon-on-insulator FinFET technology is utilized for the IBM processor designs in the 14-nm node. This process technology has a number of unique elements that enable these prod...
Autor:
Jed H. Rankin, Mukesh Khare, D. A. Grosch, T. Ivers, Gary B. Bronner, Shahid Butt, Scott R. Stiffler, Daniel J. Poindexter, Daniel C. Edelstein, Tom Faure, M. D. Knox, Peng Wu, Paul D. Agnello, H.-J. Nam, Shreesh Narasimha
Publikováno v:
IBM Journal of Research and Development. 51:5-18
IBM 90-nm silicon-on-insulator (SOI) technology was used for the key chips in the System z9TM processor chipset. Along with system design, optimization of some critical features of this technology enabled the z9TM to achieve double the system perform
Autor:
E. Engbrecht, Edward P. Maciejewski, Christopher D. Sheraw, R. Divakaruni, Zhengwen Li, Allen H. Gabor, L. Economikos, Fernando Guarin, N. Zhan, H-K Lee, MaryJane Brodsky, Kenneth J. Stein, Siyuranga O. Koswatta, Y. Yang, Byeong Y. Kim, J. Hong, A. Bryant, Herbert L. Ho, Ruqiang Bao, Nicolas Breil, Babar A. Khan, E. Woodard, W-H. Lee, C-H. Lin, A. Levesque, Kevin McStay, V. Basker, Viraj Y. Sardesai, C. Tran, A. Ogino, Reinaldo A. Vega, C. DeWan, Shreesh Narasimha, J-J. An, Amit Kumar, A. Aiyar, Ravikumar Ramachandran, W. Wang, X. Wang, W. Nicoll, D. Hoyos, A. Friedman, Barry Linder, Yongan Xu, E. Alptekin, Cathryn Christiansen, S. Polvino, Han Wang, Scott R. Stiffler, G. Northrop, S. Saudari, J. Rice, Saraf Iqbal Rashid, Sunfei Fang, Michael V. Aquilino, Z. Ren, B. Kannan, Geng Wang, Noah Zamdmer, T. Kwon, Paul D. Agnello, Hasan M. Nayfeh, S. Jain, Robert R. Robison, M. Hasanuzzaman, J. Cai, L. Lanzerotti, D. Wehelle-Gamage, Basanth Jagannathan, J. Johnson, E. Kaste, Kai Zhao, Huiling Shang, Carl J. Radens, Shariq Siddiqui, Y. Ke, D. Ferrer, Ximeng Guan, D. Conklin, K. Boyd, K. Henson, Siddarth A. Krishnan, Bernard A. Engel, H. Dong, S. Mahajan, Unoh Kwon, Dominic J. Schepis, William Y. Chang, Liyang Song, Brian J. Greene, Chengwen Pei, S.-J. Jeng, Clevenger Leigh Anne H, Vijay Narayanan, C. Zhu, Wai-kin Li, Henry K. Utomo, Wei Liu, Dureseti Chidambarrao
Publikováno v:
2014 IEEE International Electron Devices Meeting.
We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4th generat
Autor:
Rajeev Malik, Rishikesh Krishnan, Sunfei Fang, Bernhard Wunder, Kevin McStay, Yanli Zhang, Sadanand V. Deshpande, Douglas Daley, Herbert L. Ho, Sneha Gupta, Paul C. Parries, Balaji Jayaraman, Sungjae Lee, Puneet Goyal, John E. Barth, Scott R. Stiffler, Paul D. Agnello, Subramanian S. Iyer
Publikováno v:
ICICDT
In this paper, we present a systematic performance study and modeling of on-chip deep trench (DT) decoupling capacitors for high-performance SOI microprocessors. Based on system-level simulations, it is shown that the DT decoupling capacitors (decap)
Autor:
Herbert L. Ho, Jinping Liu, Paul C. Parries, Norman Robson, Jing Li, Puneet Goyal, S.S. Iyer, Ming Yin, Babar A. Khan, Zhengwen Li, Paul D. Agnello, K. V. Hawkins, Sunfei Fang, T. Weaver, Scott R. Stiffler, Kevin McStay, Rishikesh Krishnan, W. Davies, R. Takalkar, T. Kirihata, Sami Rosenblatt, S. Galis, A. Blauberg, Shreesh Narasimha, Michael P. Chudzik, Amanda L. Tessier, William K. Henson, W. Kong, Edward P. Maciejewski, Alberto Cestero, Nauman Zafar Butt, Joseph Ervin, S. Gupta, Jeyaraj Antony Johnson, S. Rombawa, Sungjae Lee, J. Barth, Ying Zhang
Publikováno v:
2010 International Electron Devices Meeting.
We present industry's smallest eDRAM cell and the densest embedded memory integrated into the highest performance 32nm High-K Metal Gate (HKMG) SOI based logic technology. The cell is aggressively scaled at 58% (vs. 45nm) and features the key innovat
Autor:
Russell H. Arndt, Ashima B. Chakravarti, Anthony G. Domenicucci, Amanda L. Tessier, Jinping Liu, Sunfei Fang, Kevin McStay, Zhengwen Li, Randolph F. Knarr, S. Lee, Joseph F. Shepard, Herbert L. Ho, A. Arya, R. Venigalla, W. Davies, R. Takalkar, Rishikesh Krishnan, Paul C. Parries, B. Morgenfeld, Xin Li, S. Gupta, Michael P. Chudzik, Scott R. Stiffler, Puneet Goyal, Babar A. Khan, Sadanand V. Deshpande, J. Dadson, Scott D. Allen
Publikováno v:
2010 IEEE International SOI Conference (SOI).
In this paper, we describe the unique scaling challenges, critical sources of variation, and the potential trench leakage mechanisms of 32nm trench capacitors that utilize high-к/metal electrode materials. This is the first eDRAM technology that has
Publikováno v:
Journal of Applied Physics. 71:4820-4825
The thermal relaxation of SiGe films deposited by ultrahigh‐vacuum chemical vapor deposition was studied by annealing the films for times up to 21/2 h at a temperature of 950 °C. Strain relaxation was determined by misfit dislocation density obtai
Autor:
S.S. Iyer, Ravi M. Todi, Rajeev Malik, Erik A. Nelson, Rishikesh Krishnan, Sunfei Fang, Byeong Y. Kim, R. Takalkar, D. Anand, Oh-Jung Kwon, Michael P. Chudzik, Nauman Zafar Butt, Scott R. Stiffler, Herbert L. Ho, Joseph Ervin, Siddarth A. Krishnan, Babar A. Khan, Alberto Cestero, Gregory G. Freeman, Geng Wang, Karen A. Nummy, J. Sim, Amanda L. Tessier, Jin Liu, W. Kong, Paul C. Parries, Kevin McStay
Publikováno v:
2009 IEEE International Electron Devices Meeting (IEDM).
A high performance embedded DRAM with deep trench capacitor and high performance SOI logic has been deployed in 45nm and 32nm technology nodes. Following a yield ramp of the sub-2ns latency 45nm technology, we present, for the first time, a 32nm eDRA
Autor:
David L. Harame, James H. Comfort, E. de Fresart, Scott R. Stiffler, Bernard S. Meyerson, C.L. Stanis
Publikováno v:
Journal of Applied Physics. 70:1416-1420
The thermal stability of SiGe films deposited by ultrahigh‐vacuum chemical vapor deposition was studied. Various Ge compositional profiles, including boxes, trapezoids, and triangles were examined. Planar‐view transmission electron microscopy was