Zobrazeno 1 - 10
of 25
pro vyhledávání: '"Scott Luning"'
Autor:
Scott Luning, Jon Kluth, Girish Bohra, Xiaobo Chen, Suraj K. Patil, Sherry Straub, Mitsuhiro Togo, Dina H. Triyoso, Anil Kumar, Alex Chen, Ryan Sporer, Kasun Punchihewa, Bob Mulfinger, Rohit Pal, X. Zhang, Jeremy A. Wahl, Amy Child, Laegu Kang, Rick Carter
Publikováno v:
ECS Transactions. 69:103-110
After decades of research, high-k metal gate has been successfully integrated into CMOS starting with 45nm node. High-k can be integrated using gate first or gate last integration. To continue scaling, the industry has chosen two integration approach
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9574743996ec5e2c320cb27e5003f17b
https://doi.org/10.1149/06905.0103ecst
https://doi.org/10.1149/06905.0103ecst
Autor:
Shom Ponoth, Arvind Kumar, J. Kuss, Pranita Kulkarni, Frederic Boeuf, Ali Khakifirooz, Balasubramanian S. Haran, Effendi Leobandung, Kangguo Cheng, Qing Liu, Mukesh Khare, Maud Vinet, Scott Luning, Masami Hane, T. Yamamoto, Nicolas Loubet, Prasanna Khare, Walter Kleemeier, Terence B. Hook, Frederic Monsieur, Mariko Takayanagi, Thomas Skotnicki, Stephane Monfray, Huiming Bu, Ron Sampson, Kazunari Ishimaru, Sanjay Mehta, Jin Cai, Bruce B. Doris, Atsushi Yagishita
Publikováno v:
ECS Transactions. 34:37-42
We report fully-depleted UTBB devices with a gate length (LG) of 25nm and BOX thickness (TBOX) at 25nm, fabricated with a 22nm technology ground rule, featuring conventional gate first high-K/metal and raised source/drain (RSD) process. Competitive d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::148eaf103c2cef33d9dfa1a0b2d0786f
https://doi.org/10.1149/1.3567556
https://doi.org/10.1149/1.3567556
Autor:
Scott Luning, Ashima B. Chakravarti, Z. Zhu, A. Gehring, Anita Madan, Alexander Reznicek, Guangrui Xia, R. Takalkar, Dan Mocuta, Dominic J. Schepis, B. Yang, Thomas N. Adam, E. Leobandung, Ka Kong Chan, J. Faltermeier, J. P. de Souza, Zhibin Ren, John Li, Rohit Pal, Eric C. Harley, Edward P. Maciejewski, Brian J. Greene, Abhishek Dube, D.-G. Park, M. Cai, D. K. Sadana, Linda Black, Bin Yang, Johan W. Weijtmans, G. Pei
Publikováno v:
ECS Transactions. 16:317-323
Summary In summary, this work demonstrates that integrating ISPD eSi:C stressor in the thick-oxide long-channel nMOS source and drain is feasible. Key challenges lie in both high-quality ISPD eSi:C EPI development and modification of the conventional
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::479e8a9b274b3fc5f4f083f4de0812c6
https://doi.org/10.1149/1.2986789
https://doi.org/10.1149/1.2986789
Autor:
D. Greenlaw, Jon D. Cheek, Manfred Horstmann, Christoph Schwan, Markus Lenski, Peter Huebler, Scott Luning, R. van Bentum, N. Kepler, Matthias Schaller, James F. Buller, Hartmut Ruelke, Kai Frohberg, Gert Burbach, Rolf Stephan, J. Klais, S. Krishnan, Jörg Hohage, Andy Wei, Th. Feudel, Michael Raab, G. Grasshoff, Karsten Wieczorek, Martin Gerhardt
Publikováno v:
Materials Science and Engineering: B. :3-8
Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::abb84ee304cfa2679774d71a12b2b9b9
https://doi.org/10.1016/j.mseb.2004.07.077
https://doi.org/10.1016/j.mseb.2004.07.077
Autor:
M. Celik, Michel Haond, R. Sampson, S. Kanakasabapathy, Balasubramanian S. Pranatharthi Haran, L. Grenouillet, Scott Luning, T. Skotnicki, Walter Kleemeier, Pierre Morin, Shom Ponoth, S. Guillaumet, Chanemougame Daniel, R. Johnson, J. L. Bataillon, T. Levin, Olivier Weber, Ali Khakifirooz, James Chingwei Li, Romain Wacquez, H. Kothari, Gen Tsutsui, Frederic Allibert, Lisa F. Edge, Kangguo Cheng, Mukesh Khare, Swati Mehta, Nicolas Loubet, Emmanuel Josse, M. Vinet, Huiming Bu, F. Chafik, J. Gimbert, Toshiharu Nagumo, Y. Le Tiec, Qing Liu, Bruce B. Doris, O. Faynot, J. Kuss
Publikováno v:
2013 IEEE International Electron Devices Meeting.
We report, for the first time, high performance Ultra-thin Body and Box (UTBB) FDSOI devices with a gate length (LG) of 20nm and BOX thickness (TBOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::53eff7a8ac1cf8b251f5508b9063d701
https://doi.org/10.1109/iedm.2013.6724592
https://doi.org/10.1109/iedm.2013.6724592
Autor:
Chung-Hsi Wu, Sen Liu, Kangguo Cheng, Maud Vinet, Steven J. Holmes, Wu-Song Huang, Qing Liu, Kuang-Jung Chen, Scott Luning, Matt Colburn, Bruce B. Doris, Ranee Kwong, Laurent Grenouillet, Greg Breyta
Publikováno v:
SPIE Proceedings.
As an option to traditional positive or negative photoresist, hybrid resist has been developed to provide an alternative way to create small trench features, at the range of 20-60 nm, by generating with a single expose, with both positive and negativ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c31bb8ef1330cfcf6841b35ffffaa7c0
https://doi.org/10.1117/12.2011515
https://doi.org/10.1117/12.2011515
Autor:
H. He, Kangguo Cheng, Yu Zhu, Sean Teehan, Toshiharu Nagumo, M. Terrizzi, A. Upham, James Chingwei Li, R. Sampson, Walter Kleemeier, G. Pfeiffer, Alexander Reznicek, Lisa F. Edge, Alex Hubbard, L. Grenouillet, Prasanna Khare, Qing Liu, R. Johnson, Bich-Yen Nguyen, Pouya Hashemi, J. Kuss, Ghavam G. Shahidi, Scott Luning, Thomas N. Adam, Romain Wacquez, Frederic Allibert, Sebastian Naczas, T. Wu, Y. Le Tiec, S. Holmes, Bruce B. Doris, T. Levin, Ali Khakifirooz, Maud Vinet, Tak H. Ning, A. Inada, Z. Zhu, Nicolas Loubet, Anita Madan, J. Gimbert, Mukesh Khare, N. Klymko, Robert H. Dennard
Publikováno v:
2012 International Electron Devices Meeting.
For the first time, we report high performance hybrid channel ETSOI CMOS by integrating strained SiGe-channel (cSiGe) PFET with Si-channel NFET at 22nm groundrules. We demonstrate a record high speed ring oscillator (fan-out = 3) with delay of 8.5 ps
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5c9ce498df4b8587c378d74fc536353a
https://doi.org/10.1109/iedm.2012.6479063
https://doi.org/10.1109/iedm.2012.6479063
Autor:
Raghavasimhan Sreenivasan, J. Kuss, Ali Khakifirooz, Y. Le Tiec, Shom Ponoth, Nicolas Loubet, Bruce B. Doris, Zhibin Ren, Scott Luning, Kangguo Cheng, J. Gimbert, L. Grenouillet, Romain Wacquez, M. Vinet, Pranita Kulkarni, Qing Liu, Davood Shahrjerdi, T. Nagumo, J. Cai, Alexander Reznicek
Publikováno v:
CICC
We review the basics of the extremely thin SOI (ETSOI) technology and how it addresses the main challenges of the CMOS scaling at the 20-nm technology node and beyond. The possibility of V T tuning with backbias, while keeping the channel undoped, op
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8c0b93eef4d2c302b2ae91b41c52864c
https://doi.org/10.1109/cicc.2012.6330618
https://doi.org/10.1109/cicc.2012.6330618
Autor:
Walter Schwarzenbach, Davood Shahrjerdi, Prasanna Khare, Nicolas Loubet, Sebastian Naczas, Kangguo Cheng, Yu Zhu, Cecile Aulnette, Swati Mehta, Bruce B. Doris, T. Yamamoto, Qing Liu, Stefan Schmitz, J. Kuss, Vamsi Paruchuri, Scott Luning, Ghavam G. Shahidi, H. He, Alexander Reznicek, Pouya Hashemi, James Chingwei Li, Thomas N. Adam, Shom Ponoth, Toshiharu Nagumo, S. Holmes, Bich-Yen Nguyen, T. Levin, Ali Khakifirooz, Anita Madan, Raghavasimhan Sreenivasan, J. Gimbert, Mukesh Khare, Frederic Monsieur, Pranita Kulkarni, Nicolas Daval, Z. Zhu
Publikováno v:
2012 Symposium on VLSI Technology (VLSIT).
High-performance strain-engineered ETSOI devices are reported. Three methods to boost the performance, namely contact strain, strained SOI (SSDOI) for NFET, and SiGe-on-insulator (SGOI) for PFET are examined. Significant performance boost is demonstr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::26e971d12424a72d4499469a4835d3ed
https://doi.org/10.1109/vlsit.2012.6242489
https://doi.org/10.1109/vlsit.2012.6242489
Autor:
Sanjay Mehta, M. Vinet, Bruce B. Doris, Kangguo Cheng, Nicolas Posseme, Y. Le Tiec, Balasubramanian S. Pranatharthi Haran, Raghavasimhan Sreenivasan, Terence B. Hook, Mukesh Khare, Amit Kumar, Qing Liu, Nicolas Loubet, Scott Luning, V. Destefanis, S. Kanakasabapathy, Pranita Kulkarni, T. Levin, L. Grenouillet, Ali Khakifirooz, N. Berliner, Stefan Schmitz, J. Kuss, Ghavam G. Shahidi, Shom Ponoth
Publikováno v:
IEEE 2011 International SOI Conference.
Two implantation based schemes were explored for ETSOI NFET devices targeted for the 20nm node. Amorphization of the thin SOI is a key issue for the implant pre RSD scheme. This can be alleviated by implanting through liner. Variability is the key is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e664a80b7ace29a7775eaf7c4d5c2a84
https://doi.org/10.1109/soi.2011.6081679
https://doi.org/10.1109/soi.2011.6081679