Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Scott K. Pozder"'
Autor:
Jeff Siddiqui, Scott K. Pozder, Gaddi Haase, Karsten Beckmann, P. Justison, Tom Kopley, Martin Anselm, Matt Ring
Publikováno v:
2017 IEEE International Integrated Reliability Workshop (IIRW).
Are the fields of fracture mechanics, rheology, etc. good enough to address issues In package reliability? No: JEDEC specs all based on DIP wirebond packages. Are we using results from these fields enough or most effectively? Not addressed. Biggest d
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18:450-460
Emerging 3-D multistrata system integration offers the capability for high density interstratum interconnects that have short lengths and low parasitics. However, 3-D integration is only one way to accomplish system integration and it must compete ag
Publikováno v:
IEEE Transactions on Components and Packaging Technologies. 33:56-63
Three-dimensional (3D) interconnection technology offers several electrical advantages, including reduced signal delay, reduced interconnect power, and design flexibility. 3D integration relies on through-silicon vias (TSVs) and the bonding of multip
Autor:
Robert E. Jones, Scott K. Pozder, Syed M. Alam, Ritwik Chatterjee, Ioannis Savidis, Ankur Jain
Publikováno v:
Microelectronics Journal. 41:9-16
The integration of chips in the third dimension has been explored to address various physical and system level limitations currently undermining chip performance. In this paper, we present a comprehensive analysis of the electrical properties of thro
Publikováno v:
Journal of Electronic Materials. 35:1025-1031
A bump shear test is disclosed for evaluating the mechanical integrity of low-k interconnect stacks in an integrated circuit which includes a die test structure (11) having a stiff structural component (501, 502) positioned above and affixed to a con
Publikováno v:
ISQED
Each stratum in a 3D chip usually requires a unique mask set which increases the mask cost for a multi-strata chip compared to its 2D counterpart. We present a novel design technique using reciprocal design symmetry (RDS) that allows a mask set (or a
Publikováno v:
ASME 2009 InterPACK Conference, Volume 1.
While the stacking of multiple strata to produce 3D integrated circuits improves interconnect length and hence reduces power and latency, it also results in the exacerbation of the thermal management challenge due to the increased power density. Ther
Autor:
Ritwik Chatterjee, Scott K. Pozder, Hannes Kostner, Ankur Jain, Eddie Acosta, Martin Sobczak, Senthil Kanagavel, Gerhard Hillmann, Bill Marlin, Gerald Kreindl, Stefan Pargfrieder, Robert E. Jones, Zhihong Huang
Publikováno v:
2008 International Interconnect Technology Conference.
The simultaneous formation of Cu/Sn microconnects and an adhesive bond during wafer level thermal compression bonding was evaluated using a 3D enabled single metal level test die and wafer. The wafer level bond process relied on locally dispensed adh
Autor:
D.A. Gajewski, Varughese Mathew, Robert E. Jones, Ritwik Chatterjee, Zhihong Huang, Scott K. Pozder, Eddie Acosta, P. Justison, Ankur Jain, R. Hernandez
Publikováno v:
2008 58th Electronic Components and Technology Conference.
There is significant interest in 3D interconnect technology due to its capability to provide fast, efficient inter-die interconnects at a minimum package footprint. Intermetallic Cu-Sn bonding has been widely investigated for 3D interconnects. Howeve
Publikováno v:
2008 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems.
3D interconnect technology has attracted significant interest in the recent past as a means for enabling faster and more efficient integrated circuits (ICs). 3D integration relies on through-silicon vias (TSVs) and bonding of multiple active layers.