Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Scott D. Stansberry"'
Autor:
Scott D. Stansberry, Kenneth A. LaBel, Christina Seidleck, Megan C. Casey, J. A. Maharrey, Dante Gamboa, Jonathan A. Pellish
Publikováno v:
IEEE Transactions on Nuclear Science. 68:402-409
We are presenting single-event effect testing results on a 22-nm fully depleted silicon-on-insulator test chip from GlobalFoundries. The 128-Mb static random access memory (SRAMs) were irradiated with heavy ions, and the results are compared to previ
Publikováno v:
IEEE Transactions on Nuclear Science. 64:637-642
Single-event transients (SETs) induced by alpha particles and heavy ions are measured and analyzed with subthreshold voltage SET characterization circuits. Using a Schmitt trigger inverter target chain fabricated in a 65-nm bulk CMOS process, SET pul
Autor:
Peter Gadfort, Matthew J. Kay, Adam R. Duncan, Jonathan R. Alhbin, Austin H. Roach, Matthew J. Gadlage, Scott D. Stansberry, Matthew R. Halstead
Experimental data from alpha particle, neutron, and heavy ion testing are discussed and analyzed from a sub-threshold voltage SET characterization circuit. Using a Schmitt trigger inverter target chain fabricated in a 28-nm bulk CMOS process, SET pul
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::da4e76c287a68a67e8826b1ec1d1ce63
https://zenodo.org/record/1273859
https://zenodo.org/record/1273859
Autor:
Hyun-Chul Kim, Ken LaBel, M. Friendlich, C. Poivey, Scott D. Stansberry, David J. Petrick, Melanie D. Berg
Publikováno v:
IEEE Transactions on Nuclear Science. 54:2137-2140
We present guidelines to reduce risk to an acceptable level when using complex devices in space applications. An example of application for the use of Virtex 4 field programmable gate array (FPGA) on express logistic carrier(ELC) project is presented
Autor:
R. Naseer, Scott D. Stansberry, Lloyd W. Massengill, M.A. Bajura, J. Sondeen, S. DasGupta, Y. Boulghassoul, Arthur F. Witulski, Jeffrey Draper, John Damoulakis
Publikováno v:
IEEE Transactions on Nuclear Science. 54:935-945
A mathematical bit error rate (BER) model for upsets in memories protected by error-correcting codes (ECCs) and scrubbing is derived. This model is compared with expected upset rates for sub-100-nm SRAM memories in space environments. Because sub-100
Autor:
A. Phan, Melanie D. Berg, Ken LaBel, M. Friendlich, Hak Kim, C. Poivey, Scott D. Stansberry, David J. Petrick, Christina Seidleck, T.L. Irwin
Publikováno v:
2007 9th European Conference on Radiation and Its Effects on Components and Systems.
We present heavy ion and proton SEE data on Xilinx Virtex-4 FPGA XC4VFX60. XC4VFX60 FPGA embeds two power PC405 processors. Purpose of these tests was the validation of this FPGA for use on hubble space telescope (HST) next servicing mission.