Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Scott C. Best"'
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 67:4970-4983
As an important hardware security primitive, the true random number generator (TRNG) has been widely utilized in many critical applications. The performance and security of TRNGs are always dominant features that determine the usability of a TRNG sch
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d540ca7f9b37bd07be595cbb915ca670
https://doi.org/10.1109/tcsi.2020.3019030
https://doi.org/10.1109/tcsi.2020.3019030
Autor:
Scott C. Best, Xiaolin Xu
Publikováno v:
ICCAD
True random number generator (TRNG) is an important primitive in cryptographic applications. In this paper, a TRNG based on a self-timed ring structure is presented, the basic elements of the ring is a realization of a chaotic cellular automata topol
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::07dccc0459a55f2783cc08d8b0a0aa67
https://doi.org/10.1109/iccad45719.2019.8942050
https://doi.org/10.1109/iccad45719.2019.8942050
A ring-shaped logic circuit is proposed here as a robust design for a True Random Number Generator (TRNG). Most existing TRNGs rely on physical noise as a source of randomness, where the underlying idealized deterministic system is simply oscillatory
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::22baede63daaffcabd2808ea42bcc364
Autor:
Hai Lan, Tom Giovannini, Scott C. Best, Don Mullen, David Secker, Wendemagegnehu T. Beyene, Ming Li
Publikováno v:
2013 IEEE 63rd Electronic Components and Technology Conference.
This paper presents signal and power integrity analysis of a double-sided flip-chip package. A memory controller is attached on one side of the organic substrate, and 3D-stacked, disaggregated memory chips, integrated with through silicon vias (TSVs)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1faece4b40c614a57229c988da03395b
https://doi.org/10.1109/ectc.2013.6575544
https://doi.org/10.1109/ectc.2013.6575544
Autor:
Chris Madden, Yi Lu, Liji Gopalakrishnan, Kashinath Prabhu, Scott C. Best, Kambiz Kaviani, Ravi Kollipara, Pravin Kumar Venkatesan, Ganapathy E. Kumar, Sanath Bangalore, Lei Luo, K. Vyas, Hai Lan, Michael Bucher, Sam Chang
Publikováno v:
2013 IEEE 63rd Electronic Components and Technology Conference.
A memory system that meets the bandwidth, power efficiency, and capacity needs of future computing systems is presented in this paper. A 6.4 Gbps single-ended DDR memory interface for the controller and the DRAM was designed in a 28-nm CMOS process f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7033e1ee61c026c3925bd9b959f35ac0
https://doi.org/10.1109/ectc.2013.6575751
https://doi.org/10.1109/ectc.2013.6575751
Publikováno v:
2012 IEEE 62nd Electronic Components and Technology Conference.
This paper presents a double-sided flip-chip package. The package consists of a memory controller on one side of an organic substrate, and 3D-stacked, disaggregated memory chips, integrated with TSVs, on the opposite side. Thermal isolation is one of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a941be39901832dbb816605f974ca3c7
https://doi.org/10.1109/ectc.2012.6248934
https://doi.org/10.1109/ectc.2012.6248934
Autor:
Lei Luo, Brian S. Leibowitz, Jared L. Zerbe, Scott C. Best, Amir Amirkhany, Robert E. Palmer, John Wilson, John Eble, Nhat Nguyen
Publikováno v:
CICC
Power-efficiency results from several generations of I/O interfaces with specific goals are presented as well as the tradeoffs made within and across those designs. Foundational work in active-power reduction at a single rate for a symmetric system,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::18e575356ee22a4968fc3c781ee445b2
https://doi.org/10.1109/cicc.2011.6055367
https://doi.org/10.1109/cicc.2011.6055367
Autor:
Scott C. Best, Chuck Yuan, John Wilson, Joong-Ho Kim, Ravi Kollipara, Thomas Giovannini, Michael Ching, Ian Shaeffer, Dan Oh
Publikováno v:
2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems.
Today's high performance computing memory systems mainly consist of with DDR3 DRAMs offering 800Mb/s to 1600Mb/s data rates. Extending the performance of these main memory systems beyond the current data rate is quite challengeable as the signal inte
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aaa0eca23e6f5c15762fdeccc3106b4f
https://doi.org/10.1109/epeps.2009.5338468
https://doi.org/10.1109/epeps.2009.5338468
Autor:
William F. Stonecypher, Gong Jong Yeh, Carl W. Werner, Haw-Jyh Liaw, Jared L. Zerbe, Kevin S. Donnelly, Scott C. Best, Pak Shing Chau, T.P. Thrush
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
A 2 Gb/s/pin single-ended 4-PAM parallel bus interface uses transmit crosstalk cancellation and equalization techniques as well as integrating data receivers to improve system margin in low-cost packaging despite inherent coupling noise and data dist
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::230930cb68e73cb0c6b22f350122ae00
https://doi.org/10.1109/isscc.2001.912549
https://doi.org/10.1109/isscc.2001.912549
Autor:
Zerbe, J.L., Chau, P.S., Werner, C.W., Stonecypher, W.F., Liaw, H.J., Gong Jong Yeh, Thrush, T.P., Best, S.C., Donnelly, K.S.
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177); 2001, p66-432, 3p